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부품번호 AD679 기능
기능 14-Bit 128 kSPS Complete Sampling ADC
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AD679 데이터시트, 핀배열, 회로
a
FEATURES
AC and DC Characterized and Specified
(K, B, T Grades)
128k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
78 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 MInput Impedance
8-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Pin Compatible with AD678 12-Bit, 200 kSPS ADC
MIL-STD-883 Compliant Versions Available
14-Bit 128 kSPS
Complete Sampling ADC
AD679
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD679 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-and-hold am-
plifier (SHA), a microprocessor-compatible bus interface, a volt-
age reference, and clock generation circuitry.
The AD679 is specified for ac (or dynamic) parameters such as
S/N+D ratio, THD, and IMD, which are important in signal
processing applications. In addition, the AD679K, B, and T
grades are fully specified for dc parameters that are important in
measurement applications.
The 14 data bits are accessed in two read operations (8 + 6),
with left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input
impedance (10 M) allows direct connection to unbuffered
sources without signal degradation. Conversions can be initiated
either under microprocessor control or by an external clock
asynchronous to the system clock.
This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm that includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD679 operates from +5 V and ±12 V supplies and dissipates
560 mW (typ). The part is available in 28-lead plastic DIP,
ceramic DIP, and 44 J-leaded ceramic surface-mount packages.
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The AD679 minimizes
external component requirements by combining a high
speed sample-and-hold amplifier (SHA), ADC, 5 V refer-
ence, clock, and digital interface on a single chip. This
provides a fully specified sampling A/D function unattain-
able with discrete designs.
2. SPECIFICATIONS: The AD679K, B, and T grades provide
fully specified and tested ac and dc parameters. The AD679J,
A, and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain, and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD, and IMD) are of value in signal process-
ing applications.
3. EASE OF USE: The pinout is designed for easy board layout,
and the two-read output provides compatibility with 8-bit
buses. Factory trimming eliminates the need for calibration
modes or external trimming to achieve rated performance.
4. RELIABILITY: The AD679 utilizes Analog Devices’ mono-
lithic BiMOS technology. This ensures long-term reliability
compared to multichip and hybrid designs.
5. UPGRADE PATH: The AD679 provides the same pinout as
the 12-bit, 200 kSPS AD678 ADC.
6. The AD679 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD679/883B data sheet for detailed
specifications.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.




AD679 pdf, 반도체, 판매, 대치품
AD679
TIMING SPECIFICATIONS (All device types TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V
؎ 5%, VDD = +5 V ؎ 10%)
Parameter
Symbol
Min
Max
Unit
SC Delay
Conversion Time
Conversion Rate1
Convert Pulse Width
Aperture Delay
Status Delay
Access Time2, 3
Float Delay5
Output Delay
Format Setup
OE Delay
Read Pulse Width
Conversion Delay
EOCEN Delay
tSC 50
ns
tC 6.3 µs
tCR 7.8 µs
tCP
0.097
3.0
µs
tAD 5
20 ns
tSD 0
400 ns
tBA 10 100 ns
10 574 ns
tFD 10
80
tOD 0
tFS 100
ns
ns
ns
tOE 20
tRP 195
tCD 400
ns
ns
ns
tEO 50
ns
NOTES
1Includes acquisition time.
2Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.
3COUT = 100 pF.
4COUT = 50 pF.
5Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5. See Figure 4; COUT
= 10 pF.
Specifications subject to change without notice.
NOTES
1IN ASYNCHRONOUS MODE, STATE OF CS DOES NOT AFFECT OPERATION.
SEE THE START CONVERSION TRUTH TABLE FOR DETAILS.
2EOCEN = LOW (SEE FIGURE 3). IN SYNCHRONOUS MODE, EOC IS A THREE-
STATE OUTPUT. IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT.
3DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
Figure 1. Conversion Timing
NOTE
1EOC IS A THREE-STATE OUTPUT IN SYNCHRONOUS MODE
AND AN OPEN DRAIN OUTPUT IN ASYNCHRONOUS. ACCESS (tBA)
AND FLOAT (tFD) TIMING SPECIFICATIONS DO NOT APPLY IN
ASYNCHRONOUS MODE WHERE THEY ARE A FUNCTION OF THE
TIME CONSTANT FORMED BY THE 10pF OUTPUT CAPACITANCE
AND THE PULL-UP RESISTOR.
Figure 3. EOC Timing
TEST
ACCESS TIME HIGH Z TO LOGIC LOW 5V
FLOAT TIME LOGIC HIGH TO HIGH Z
ACCESS TIME HIGH Z TO LOGIC HIGH
FLOAT TIME LOGIC LOW TO HIGH Z
VCP
100pF
0V
0V
5V
COUT
10pF
100pF
10pF
IOL
Figure 2. Output Timing
DOUT
COUT
VCP
IOH
Figure 4. Load Circuit for Bus Timing Specifications
–4– REV. D

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AD679 전자부품, 판매, 대치품
AD679
DEFINITIONS OF SPECIFICATIONS
Nyquist Frequency
An implication of the Nyquist sampling theorem, the Nyquist
frequency of a converter is the input frequency that is one-half
the sampling frequency of the converter.
Signal-to-Noise and Distortion (S/N+D) Ratio
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic compo-
nents to the rms value of a full-scale input signal and is expressed
as a percentage or in decibels. For input signals or harmonics
above the Nyquist frequency, the aliased component is used.
Peak Spurious or Peak Harmonic Component
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n) at sum and difference frequencies of mfa Ϯ
nfb, where m, n = 0, 1, 2, 3.... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb) and the third order terms
are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
products are expressed as the decibel ratio of the rms sum of
the measured input signals to the rms sum of the distortion
terms. The two signals applied to the converter are of equal
amplitude, and the peak value of their sum is –0.5 dB from full-
scale (9.44 V p-p). The IMD products are normalized to a 0 dB
input signal.
Bandwidth
The full-power bandwidth is the input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-and-hold amplifier (SHA) is
reached. At this point, the amplitude of the reconstructed fun-
damental has degraded by less than –0.1 dB. Beyond this fre-
quency, distortion of the sampled input signal increases
significantly.
The AD679 has been designed to optimize input bandwidth,
allowing it to undersample input signals with frequencies signifi-
cantly above the converter’s Nyquist frequency.
Aperture Delay
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of start convert (SC) to when
the input signal is held for conversion. In synchronous mode,
chip select (CS) should be LOW before SC to minimize aper-
ture delay.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
Input Setting Time
Settling time is a function of the SHA’s ability to track fast slew-
ing signals. This is specified as the maximum time required in
track mode after a full-scale step input to guarantee rated con-
version accuracy.
Differential Nonlinearity (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
linearity is the deviation from this ideal value. It is often speci-
fied in terms of resolution for which no missing codes (NMC)
are guaranteed.
Integral Nonlinearity (INL)
The ideal transfer function for a linear ADC is a straight line
drawn between zero and full scale. The point used as zero occcurs
1/2 LSB before the first code transition. Full scale is defined as
a level 1 1/2 LSB beyond the last code transition. Integral linear-
ity error is the worst case deviation of a code from the straight
line. The deviation of each code is measured from the middle of
that code.
Note that the linearity error is not user adjustable.
Power Supply Rejection
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
Temperature Drift
This is the maximum change in the parameter from the initial
value (@ 25°C) to the value at TMIN or TMAX.
Unipolar Zero Error
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the devia-
tion of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
Bipolar Zero Error
In the bipolar mode, the major carry transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value
1/2 LSB below analog ground. Bipolar zero error is the devia-
tion of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
Gain Error
The last transition should occur at an analog value 1 1/2 LSB
below the nominal full scale (9.9991 V for a 0 V to 10 V range,
4.9991 V for a Ϯ5 V range). The gain error is the deviation of
the actual level at the last transition from the ideal level with the
zero error trimmed out. This error can be adjusted as shown in
the Input Connections and Calibration section.
REV. D
–7–

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