PDF AD684 Data sheet ( Hoja de datos )

Número de pieza	AD684
Descripción	Four-Channel Sample-and-Hold Amplifier
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES Four Matched Sample-and-Hold Amplifiers Independent Inputs, Outputs and Control Pins 500 ns Hold Mode Settling 1 ␮s Maximum Acquisition Time to 0.01% Low Droop Rate: 0.01 ␮V/␮s Internal Hold Capacitors 75 ps Maximum Aperture Jitter Low Power Dissipation: 430 mW 0.3" Skinny DIP Package MIL-STD-883 Compliant Versions Available Four-Channel Sample-and-Hold Amplifier AD684 FUNCTIONAL BLOCK DIAGRAM PRODUCT DESCRIPTION The AD684 is a monolithic quad sample-and-hold amplifier (SHA). It features four complete sampling channels, each controlled by an independent hold command. Each SHA is complete with an internal hold capacitor. The high accuracy SHA channels are self-contained and require no external components or adjustments. The AD684 is manufactured on a BiMOS process which provides a merger of high performance bipolar circuitry and low power CMOS logic. The AD684 is ideal for high performance, multichannel data acquisition systems. Each SHA channel can acquire a signal in less than 1 µs and retain the held value with a droop rate of less than 0.01 µV/µs. Excellent linearity and ac performance make the AD684 an ideal front end for high speed 12- and 14-bit ADCs. The AD684 has a self-correcting architecture that minimizes hold mode errors and insures accuracy over temperature. Each channel of the AD684 is capable of sourcing 5 mA and incorporates output short circuit protection. The AD684 is specified for three temperature ranges. The J grade device is specified for operation from 0 to +70°C, the A grade from –40°C to +85°C and the S grade from –55°C to +125°C. PRODUCT HIGHLIGHTS 1. Fast acquisition time (1 µs) and low aperture jitter (75 ps) make the AD684 the best choice for multiple channel data acquisition systems. 2. Monolithic construction insures excellent interchannel matching in terms of timing and accuracy, as well as high reliability. 3. Independent inputs, outputs and sample-and-hold controls allow user flexibility in system architecture. 4. Low droop (0.01 µV/µs) and internally compensated hold mode error results in superior system accuracy. 5. The AD684’s fast settling time and low output impedance make it ideal for driving high speed analog to digital converters such as the AD578, AD674, AD7572 and the AD7672. 6. The AD684 is available in versions compliant with MIL- STD-883. Refer to the Analog Devices Military Products Databook or current AD684/883B data sheet for detailed specifications. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 1 page AD684 DEFINITIONS OF SPECIFICATIONS Acquisition Time — The length of time that the SHA must remain in the sample mode in order to acquire a full-scale input step to a given level of accuracy. Small Signal Bandwidth — The frequency at which the held output amplitude is 3 dB below the input amplitude, under an input condition of a 100 mV p-p sine wave. Full Power Bandwidth — The frequency at which the held output amplitude is 3 dB below the input amplitude, under an input condition of a 10 V p-p sine wave. Effective Aperture Delay — The difference between the switch delay and the analog delay of the SHA channel. A negative number indicates that the analog portion of the overall delay is greater than the switch portion. This effective delay represents the point in time, relative to the hold command, that the input signal will be sampled. Aperture Jitter — The variations in aperture delay for successive samples. Aperture jitter puts an upper limit on the maximum frequency that can be accurately sampled. Hold Settling Time —The time required for the output to settle to within a specified level of accuracy of its final held value after the hold command has been given. Droop Rate — The drift in output voltage while in the hold mode. Feedthrough — The attenuated version of a changing input signal that appears at the output when the SHA is in the hold mode. Hold Mode Offset — The difference between the input signal and the held output. This offset term applies only in the hold mode and includes the error caused by charge injection and all other internal offsets. It is specified for an input of 0 V. Tracking Mode Offset — The difference between the input and output signals when the SHA is in the track mode. Nonlinearity — The deviation from a straight line on a plot of input vs. (held) output as referenced to a straight line drawn between endpoints, over an input range of –5 V and +5 V. Gain Error — Deviation from a gain of +1 on the transfer function of input vs. held output. Interchannel Isolation — The level of crosstalk between adjacent channels while in the sample (track) mode with a full scale 100 kHz input signal. Interchannel Aperture Offset — The variation in aperture time between the four channels for a simultaneous hold command. Differential Offset — The difference in hold mode offset between the four SHA channels. Power Supply Rejection Ratio — A measure of change in the held output voltage for a specified change in the positive or negative supply. Sampled dc Uncertainty — The internal rms SHA noise that is sampled onto the hold capacitor. Hold Mode Noise — The rms noise at the output of the SHA while in the hold mode, specified over a given bandwidth. Total Output Noise — The total rms noise that is seen at the output of the SHA while in the hold mode. It is the rms summation of the sampled dc uncertainty and the hold mode noise. Output Drive Current — The maximum current the SHA can source (or sink) while maintaining a change in hold mode offset of less than 2.5 mV. FUNCTIONAL DESCRIPTION The AD684 is a complete quad sample-and-hold amplifier that provides high speed sampling to 12-bit accuracy in less than 1µs. The AD684 is completely self-contained, including on-chip hold capacitors, and requires no external components or adjustments to perform the sampling function. Each SHA channel can operate independently, having its own input, output and sample/hold command. Both inputs and outputs are treated as single ended signals, referred to common. The AD684 utilizes a proprietary circuit design which includes a self-correcting architecture. This sample-and-hold circuit corrects for internal errors after the hold command has been given, by compensating for amplifier gain and offset errors, and charge injection errors. Due to the nature of the design, the SHA output in the sample mode is not intended to provide an accurate representation of the input. However, in hold mode, the internal circuitry is reconfigured to produce an accurately held version of the input signal. To the right is a block diagram of the AD684. REV. A –5– Functional Block Diagram 5 Page

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