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AD698 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD698은 전자 산업 및 응용 분야에서
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부품번호 AD698 기능
기능 Universal LVDT Signal Conditioner
제조업체 Analog Devices
로고 Analog Devices 로고


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AD698 데이터시트, 핀배열, 회로
a
FEATURES
Single Chip Solution, Contains Internal Oscillator and
Voltage Reference
No Adjustments Required
Interfaces to Half-Bridge, 4-Wire LVDT
DC Output Proportional to Position
20 Hz to 20 kHz Frequency Range
Unipolar or Bipolar Output
Will Also Decode AC Bridge Signals
Outstanding Performance
Linearity: 0.05%
Output Voltage: ؎11 V
Gain Drift: 20 ppm/؇C (typ)
Offset Drift: 5 ppm/؇C (typ)
Universal
LVDT Signal Conditioner
AD698
FUNCTIONAL BLOCK DIAGRAM
AMP
VOLTAGE
REFERENCE
OSCILLATOR
AD698
B
A
B
FILTER
AMP
A
PRODUCT DESCRIPTION
The AD698 is a complete, monolithic Linear Variable Differen-
tial Transformer (LVDT) signal conditioning subsystem. It is
used in conjunction with LVDTs to convert transducer mechan-
ical position to a unipolar or bipolar dc voltage with a high de-
gree of accuracy and repeatability. All circuit functions are
included on the chip. With the addition of a few external passive
components to set frequency and gain, the AD698 converts the
raw LVDT output to a scaled dc signal. The device will operate
with half-bridge LVDTs, LVDTs connected in the series op-
posed configuration (4-wire), and RVDTs.
The AD698 contains a low distortion sine wave oscillator to
drive the LVDT primary. Two synchronous demodulation
channels of the AD698 are used to detect primary and second-
ary amplitude. The part divides the output of the secondary by
the amplitude of the primary and multiplies by a scale factor.
This eliminates scale factor errors due to drift in the amplitude
of the primary drive, improving temperature performance and
stability.
The AD698 uses a unique ratiometric architecture to eliminate
several of the disadvantages associated with traditional ap-
proaches to LVDT interfacing. The benefits of this new cir-
cuit are: no adjustments are necessary; temperature stability is
improved; and transducer interchangeability is improved.
The AD698 is available in two performance grades:
Grade
AD698AP
AD698SQ
Temperature Range
–40°C to +85°C
–55°C to +125°C
Package
28-Pin PLCC
24-Pin Cerdip
PRODUCT HIGHLIGHTS
1. The AD698 offers a single chip solution to LVDT signal
conditioning problems. All active circuits are on the mono-
lithic chip with only passive components required to com-
plete the conversion from mechanical position to dc voltage.
2. The AD698 can be used with many different types of posi-
tion sensors. The circuit is optimized for use with any
LVDT, including half-bridge and series opposed, (4 wire)
configurations. The AD698 accommodates a wide range of
input and output voltages and frequencies.
3. The 20 Hz to 20 kHz excitation frequency is determined by a
single external capacitor. The AD698 provides up to 24 volts
rms to differentially drive the LVDT primary, and the
AD698 meets its specifications with input levels as low as
100 millivolts rms.
4. Changes in oscillator amplitude with temperature will not af-
fect overall circuit performance. The AD698 computes the
ratio of the secondary voltage to the primary voltage to deter-
mine position and direction. No adjustments are required.
5. Multiple LVDTs can be driven by a single AD698 either in
series or parallel as long as power dissipation limits are not
exceeded. The excitation output is thermally protected.
6. The AD698 may be used as a loop integrator in the design of
simple electromechanical servo loops.
7. The sum of the transducer secondary voltages do not need to
be constant.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD698 pdf, 반도체, 판매, 대치품
AD698
Typical Characteristics (at +25°C and VS = ±15 V unless otherwise noted)
240
200
160 GAIN PSRR 15–18V
120
80
40 GAIN PSRR 12–15V
20
OFFSET PSRR 12–15V
0
–20
–60 –40 –20
OFFSET PSRR 15–18V
0 20 40 60 80
TEMPERATURE – °C
100 120 140
Figure 1. Gain and Offset PSRR vs. Temperature
120
80
40
20
0
–20
–40
–60
–80
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – °C
Figure 3. Typical Gain Drift vs. Temperature
0
–05 OFFSET CMRR ± 3V
–10
–15
–20
–25
–30
GAIN CMRR ± 3V
–35
–40
–45
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – °C
Figure 2. Gain and Offset CMRR vs. Temperature
20
15
10
5
0
–5
–10
–15
–20
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – °C
Figure 4. Typical Offset Drift vs. Temperature
–4– REV. B

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AD698 전자부품, 판매, 대치품
AD698
Multiply the primary excitation voltage by the VTR to get
the expected secondary voltage at mechanical full scale. For
example, for an LVDT with a sensitivity of 2.4 mV/V/mil and
a full scale of ± 0.1 inch, the VTR = 0.0024 V/V/Mil × 100
mil = 0.24. Assuming the maximum excitation of 3.5 V rms,
the maximum secondary voltage will be 3.5 V rms × 0.24 =
0.84 V rms, which is in the acceptable range.
Conversely the VTR may be measured explicitly. With the
LVDT energized at its typical drive level VPRI, as indicated
by the manufacturer, set the core displacement to its me-
chanical full-scale position and measure the output VSEC of
the secondary. Compute the LVDT voltage transformation
ratio, VTR. VTR = VSEC//VPRI. For the E100, VSEC = 0.72 V
for VPRI = 3 V. VTR = 0.24.
For situations where LVDT sensitivity is low, or the me-
chanical FS is a small fraction of the total stroke length, an
input excitation of more than 3.5 V rms may be needed. In
this case a voltage divider network may be placed across the
LVDT primary to provide smaller voltage for the +BIN and
–BIN input. If, for example, a network was added to divide
the B Channel input by 1/2, then the VTR should also be re-
duced by 1/2 for the purpose of component selection.
Check the power supply voltages by verifying that the peak
values of VA and VB are at least 2.5 volts less than the volt-
ages at +VS and –VS.
6. Referring to Figure 9, for VS = ± 15 V, select the value of the
amplitude determining component R1 as shown by the curve
in Figure 9.
30
25
20
15
V rms
10
5
0
0.01
0.1
1 10 100 1k
R1 – k
Figure 9. Excitation Voltage VEXC vs. R1
7. C2, C3 and C4 are a function of the desired bandwidth of
the AD698 position measurement subsystem. They should
be nominally equal values.
C2 = C3 = C4 = 10–4 Farad Hz/f5UBSYSTEM (Hz)
If the desired system bandwidth is 250 Hz, then
C2 = C3 = C4 = 10-4 Farad Hz/250 Hz = 0.4 µF
See Figures 14, 15 and 16 for more information about
AD698 bandwidth and phase characterization.
D. Set the Full-Scale Output Voltage
8. To compute R2, which sets the AD698 gain or full-scale
output range, several pieces of information are needed:
a. LVDT sensitivity, S
b. Full-scale core displacement from null, d
S × d = VTR and also equals the ratio A/B at mechanical full
scale. The VTR should be converted to units of V/V.
For a full-scale displacement of d inches, voltage out of the
AD698 is computed as
VOUT = S × d × 500 µA × R2
VOUT is measured with respect to the signal reference,
Pin 21, shown in Figure 7.
Solving for R2,
R2
=
S
×
VOUT
d × 500
µA
(1)
For VOUT = ± 10 V full-scale range (20 V span) and d = ± 0.1
inch full-scale displacement (0.2 inch span)
R2
=
2. 4
×
20 V
0.2 × 500
µA
= 83. 3 k
VOUT as a function of displacement for the above example is
shown in Figure 10.
VOUT (VOLTS)
+10
–0.1
+0.1d (INCHES)
–10
Figure 10. VOUT (±10 V Full Scale) vs. Core Displace-
ment (±0.1 Inch)
E. Optional Offset of Output Voltage Swing
9. Selections of R3 and R4 permit a positive or negative output
voltage offset adjustment.
VOS
=
1.2 V
×
R2
×
R3
1
+2
k
R4
1
+2
k
(2)
For no offset adjustment R3 and R4 should be open circuit.
To design a circuit producing a 0 V to +10 V output for a
displacement of +0.1 inch, set VOUT to +10 V, d = 0.2 inch
and solve Equation (1) for R2.
VOUT (VOLTS)
+5
–0.1
+0.1d (INCHES)
–5
Figure 11. VOUT (±5 V Full Scale) vs. Core Displacement
(±0.1 Inch)
This will produce a response shown in Figure 11.
In Equation (2) set VOS = 5 V and solve for R3 and R4. Since a
positive offset is desired, let R4 be open circuit. Rearranging
Equation (2) and solving for R3
R3 = 1.2 × R2 – 2 kΩ = 7.02 k
VOS
REV. B
–7–

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