Datasheet.kr   

AD7008 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7008은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AD7008 자료 제공

부품번호 AD7008 기능
기능 CMOS DDS Modulator
제조업체 Analog Devices
로고 Analog Devices 로고


AD7008 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 16 페이지수

미리보기를 사용할 수 없습니다

AD7008 데이터시트, 핀배열, 회로
a
CMOS
DDS Modulator
AD7008
FEATURES
Single +5 V Supply
32-Bit Phase Accumulator
On-Chip COSINE and SINE Look-Up Tables
On-Chip 10-Bit DAC
Frequency, Phase and Amplitude Modulation
Parallel and Serial Loading
Software and Hardware Power Down Options
20 MHz and 50 MHz Speed Grades
44-Pin PLCC
APPLICATIONS
Frequency Synthesizers
Frequency, Phase or Amplitude Modulators
DDS Tuning
Digital Modulation
PRODUCT DESCRIPTION
The AD7008 direct digital synthesis chip is a numerically con-
trolled oscillator employing a 32-bit phase accumulator, sine and
cosine look-up tables and a 10-bit D/A converter integrated on a
single CMOS chip. Modulation capabilities are provided for
phase modulation, frequency modulation, and both in-phase and
quadrature amplitude modulation suitable for QAM and SSB
generation.
Clock rates up to 20 MHz and 50 MHz are supported. Fre-
quency accuracy can be controlled to one part in 4 billion.
Modulation may be effected by loading registers either through
the parallel microprocessor interface or the serial interface. A
frequency-select pin permits selection between two frequencies
on a per cycle basis.
The serial and parallel interfaces may be operated independently
and asynchronously from the DDS clock; the transfer control
signals are internally synchronized to prevent metastability prob-
lems. The synchronizer can be bypassed to reduce the transfer
latency in the event that the microprocessor clock is synchro-
nous with the DDS clock.
A power-down pin allows external control of a power-down
mode (also accessible through the microprocessor interface)
The AD7008 is available in 44-pin PLCC.
PRODUCT HIGHLIGHT
1. Low Power
2. DSP/µP Interface
3. Completely Integrated
CLOCK
FSELECT
SCLK
SDATA
FUNCTIONAL BLOCK DIAGRAM
VAA GND
FS ADJUST VREF
FREQ0 32
REG
32
MUX
32
12
Σ
FREQ1
REG
32
PHASE
ACCUMULATOR
12
Σ
12
32-BIT SERIAL REGISTER
PHASE REG
IQMOD [19:10]
10
10
SIN
SIN/COS
ROM
10
COS
10
10
Σ
10
10
IQMOD [9:0]
FULLSCALE
ADJUST
10-BIT DAC
32-BIT PARALLEL REGISTER
COMMAND REG
AD7008
COMP
IOUT
IOUT
MPU INTERFACE
TRANSFER LOGIC
D0
D15 WR CS
TC0
TC3 LOAD
TEST
RESET SLEEP
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD7008 pdf, 반도체, 판매, 대치품
AD7008
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VAA, VDD to GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Commercial (J Version) . . . . . . . . . . . . . . . . . .0°C to +70°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +115°C
PLCC θJA Thermal Impedance . . . . . . . . . . . . . . . +53.8°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . +24.1°C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature
Range
AD7008AP20 –40°C to +85°C
AD7008JP50 0°C to +70°C
AD7008/PCB*
Package
Package
Description Option
44-Pin PLCC P-44A
44-Pin PLCC P-44A
1–3.5" Disk
*AD7008/PCB DDS Evaluation Kit, assembled and tested. Kit includes an
AD7008JP50.
MSB
32-BIT PARALLEL ASSEMBLY REGISTER
LSB
A WORD
D15–D0 A WORD*
A WORD
B WORD
*MOST SIGNIFICANT WORD IS LOADED FIRST
D15–D0 B WORD
Figure 5. 16-Bit Parallel Port Loading Sequence
MSB
32-BIT PARALLEL ASSEMBLY REGISTER
LSB
A BYTE
D7–D0 A BYTE*
A BYTE
B BYTE
D7–D0 B BYTE
A BYTE
B BYTE
C BYTE
D7–D0 C BYTE
A BYTE
B BYTE
C BYTE
*MOST SIGNIFICANT BYTE IS LOADED FIRST
D BYTE
D7–D0 D BYTE
Figure 6. 8-Bit Parallel Port Loading Sequence
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7008 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
PLCC
6
DGND
D8
D9
D10
D11
D12
D13
D14
D15
WR
VDD
7
17
18
PIN NO. 1 IDENTIFIER
AD7008 PLCC
TOP VIEW
(NOT TO SCALE)
40
39
29
28
VDD
RESET
SLEEP
LOAD
TC3
TC2
TC1
TC0
FSELECT
CLOCK
DGND
–4– REV. B

4페이지










AD7008 전자부품, 판매, 대치품
AD7008
Table I. Latency Table
Function
Latency
(Synchronizer Enabled CR3 = 01)
FSelect
Phase
IQ Mod
14t1
13t1
11t1
NOTE
1All latencies are reduced by 4t1 when CR3 = 1 (synchronizer disabled). 1t1 is
equal to one pipeline delay.
Table II. Source and Destination Register
TC3 TC2
TC1
TC0
LOAD
Source Register
XX
00
10
10
10
10
11
11
11
11
X X 0 N/A
X X 1 Parallel
0 0 1 Parallel
0 1 1 Parallel
1 0 1 Parallel
1 1 1 Parallel
0 0 1 Serial
0 1 1 Serial
1 0 1 Serial
1 1 1 Serial
*The Command Register can only be loaded from the parallel assembly registers.
Destination Register
N/A
COMMAND*
FREQ0
FREQ1
PHASE
IQMOD
FREQ0
FREQ1
PHASE
IQMOD
Table III. AD7008 Control Registers
Register
Size
Reset State Description
COMMAND REG* 4 Bits CR3–CR0 All Zeros
FREQ0 REG
32 Bits DB31–DB0 All Zeros
FREQ1 REG
32 Bits DB31–DB0 All Zeros
PHASE REG
12 Bits DB11–DB0 All Zeros
IQMOD REG
20 Bits DB19–DB0 All Zeros
Command Register. This is written to using the parallel assembly register.
Frequency Register 0. This defines the output frequency, when
FSELECT = 0, as a fraction of the CLOCK frequency.
Frequency Register 1. This defines the output frequency, when
FSELECT = 1, as a fraction of the CLOCK frequency.
Phase Offset Register. The contents of this register is added to the
output of the phase accumulator.
I and Q Amplitude Modulation Register. This defines the amplitude of
the I and Q signals as 10-bit twos complement binary fractions.
DB[19:10] is multiplied by the Quadrature (sine component and
multiplied by the In-Phase (cosine) component.
*On power up, the Command Register should be configured by the user for the desired mode before operation.
Table IV. Command Register Bits*
CR0 = 0
=1
CR1 = 0
=1
CR2 = 0
=1
CR3 = 0
=1
Eight-Bit Databus. Pins D15–D8 are ignored and the parallel assembly register shifts eight places left on each write.
Hence four successive writes are required to load the 32-bit parallel assembly register, Figure 6.
Sixteen-Bit Databus. The parallel assembly register shifts 16 places left on each write. Hence two successive writes are
required to load the 32-bit parallel assembly register, Figure 5.
Normal Operation.
Low Power Sleep Mode. Internal Clocks and the DAC current sources are turned off.
Amplitude Modulation Bypass. The output of the sine LUT is directly sent to the DAC.
Amplitude Modulation Enable. IQ modulation is enabled allowing AM or QAM to be performed.
Synchronizer Logic Enabled. The FSELECT, LOAD and TC3–TC0 signals are passed through a 4-stage pipeline
to synchronize them with the CLOCK, avoiding metastability problems.
Synchronizer Logic Disabled. The FSELECT, LOAD and TC3–TC0 signals bypass the synchronization logic. This
allows for faster response to the control signals.
*The Command Register can only be loaded from the parallel assembly register.
REV. B
–7–

7페이지


구       성 총 16 페이지수
다운로드[ AD7008.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
AD7001

LC2MOS GSM Baseband I/O Port

Analog Devices
Analog Devices
AD7002

LC2MOS GSM Baseband I/O Port

Analog Devices
Analog Devices

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵