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PDF AD7011 Data sheet ( Hoja de datos )
| Número de pieza | AD7011 | |
| Descripción | CMOS/ ADC p/4 DQPSK Baseband Transmit Port | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7011 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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FEATURES
Single +5 V Supply
On-Chip /4 DQPSK Modulator
Modulator Bypass Analog Mode
Root-Raised Cosine Tx Filters, ␣ = 0.35
Two 10-Bit D/A Converters
4th Order Reconstruction Filters
Differential Analog Outputs
On-Chip Ramp Up/Down Power Control
On-Chip Tx Offset Calibration
Dual Mode Operation, Analog and Digital
Very Low Power Dissipation, 30 mW typical
Power Down Mode < 10 A
On-Chip Voltage Reference
24-Pin SSOP
APPLICATIONS
American Digital Cellular Telephony
American Analog Cellular Telephony
CMOS, ADC /4 DQPSK
Baseband Transmit Port
AD7011
GENERAL DESCRIPTION
The AD7011 is a complete low power, CMOS, π/4 DQPSK
modulator with single +5 V power supply. The part is designed
to perform the baseband conversion of I and Q transmit wave-
forms in accordance with the American Digital Cellular Tele-
phone system (TIA IS-54).
The on-chip π/4 Differential Quadrature Phase Shift Keying
(DQPSK) digital modulator, which includes the root raised
cosine filters, generates I and Q data in response to the transmit
data stream. The AD7011 also contains ramp control envelope
logic to shape the I and Q output waveforms when ramping up
or down at the beginning or end of a transmit burst.
Besides providing all the necessary logic to perform π/4 DQPSK
modulation, the part also provides reconstruction filters to
smooth the DAC outputs, providing continuous time analog
outputs. The AD7011 generates differential analog outputs for
both the I and Q signals.
As it is a necessity for all digital mobile systems to use the lowest
possible power, the device has transmit and receive power-down
options. The AD7011 is housed in a space efficient 24-pin
SSOP (Shrink Small Outline Package).
MCLK
BIN (Q DATA)
Tx DATA (I DATA)
Tx CLK (FRAME)
READY
POWER
FUNCTIONAL BLOCK DIAGRAM
DGND
VDD
VAA
AGND
I
ANALOG MODE
SERIAL
INTERFACE Q
π /4 DQPSK
DIGITAL
MODULATOR
I
Q
MODULATOR
BYPASS
10-BIT
I-DAC
10-BIT
Q-DAC
RECONSTRUCTION
FILTERS
ITx
ITx
CALIBRATION CIRCUITRY
RECONSTRUCTION
FILTERS
QTx
QTx
AD7011
2.46V
REFERENCE
BOUT
BYPASS MODE1 MODE2
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD7011
ANALOG MODE TIMING (VAA = VDD = +5 V ؎ 10%. AGND = DGND = 0 V. All specifications are TMIN to TMAX unless
otherwise noted.)
Parameter
Limit at TA = –40°C to +85°C
Units
Description
t20 15
t21 15
15t1
t22 16t1
t23 15
t24 15
ns min
ns min
ns max
ns
ns min
ns min
MCLK Rising Edge to FRAME Setup Time.
MCLK Rising Edge to FRAME Hold Time.
FRAME Cycle Time.
MCLK Rising Edge to Data Setup Time.
MCLK Rising Edge to Data Hold Time.
MCLK
FRAME
I DATA
Q DATA
t20 t22
t23
t24
DB9 DB8
DB1 DB0
DB9 DB8
DB1 DB0
Figure 6. Analog Mode Serial Interface Timing
Q
MODULAR OUTPUT
DURING FTEST
t21
DB9 DB8 DB7
DB9 DB8 DB7
I
Figure 7. Modulator State During FTEST
MODE 1
0
1
0
1
Table I.
MODE 2
Operation
0 Digital TIA Mode
0 Analog Mode
1 FTEST
1 Factory Test, Reserved
Mode of Operation
Digital Mode
Analog Mode
MODE 1
0
1
MODE 2
0
0
Table II.
MCLK
3.1104 MHz
2.56 MHz
Digital Bit Rate
48.6 kHz
N/A
DAC Update Rate
N/A
160 kHz
REV. B
–5–
5 Page 
0
–10
–20
–30
–40
–50
–60
–70
–80
0.1
1 10 100
FREQUENCY – kHz
1000
Figure 13. Reconstruction Filter Frequency Response for
the I and Q DACs, MCLK = 2.56 MHz
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.2 –0.8 –0.4
0
0.4 0.8 1.2
I Channel – Volts
Figure 14. AD7011 I vs. Q Waveforms When Transmitting
Random Data
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.2 –0.8 –0.4
0
0.4 0.8 1.2
I Channel – Volts
Figure 15. AD7011 Transmit Constellation Diagram
AD7011
0
–10
–20
–30
–40
–50
–60
–70
–80
0.1
1 10 100
FREQUENCY – kHz
1000
Figure 16. Reconstruction Filter Frequency Response for
the I and Q DACs, MCLK = 3.1104 MHz
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.2 –0.8 –0.4
0
0.4 0.8 1.2
I Channel – Volts
Figure 17. AD7011 I vs. Q Waveforms Filtered by an Ideal
Root Raised Cosine Receive Filter
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.2 –0.8 –0.4
0
0.4 0.8 1.2
I Channel – Volts
Figure 18. AD7011 Constellation Diagram When Filtered
by an Ideal Root Raised Cosine Receive Filter
REV. B
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7011.PDF ] | |
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