|
|
PDF AD7243 Data sheet ( Hoja de datos )
| Número de pieza | AD7243 | |
| Descripción | LC2MOS 12-Bit Serial DACPORT | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7243 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
a
LC2MOS
12-Bit Serial DACPORT
AD7243
FEATURES
12-Bit CMOS DAC with
On-Chip Voltage Reference
Output Amplifier
Three Selectable Output Ranges
–5 V to +5 V, 0 V to +5 V, 0 V to +10 V
Serial Interface
300 kHz DAC Update Rate
Small Size: 16-Lead DIP or SOIC
Nonlinearity: ؎1/2 LSB TMIN to TMAX
Low Power Dissipation: 100 mW Typical
APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
GENERAL DESCRIPTION
The AD7243 is a complete 12-bit, voltage output, digital-to-
analog converter with output amplifier and Zener voltage refer-
ence on a monolithic CMOS chip. No external trims are
required to achieve full specified performance.
The output amplifier is capable of developing +10 V across a
2 kΩ load. The output voltage ranges with single supply opera-
tion are 0 V to +5 V or 0 V to +10 V, while an additional bipo-
lar ± 5 V output range is available with dual supplies. The ranges
are selected using the internal gain resistor.
The data format is natural binary in both unipolar ranges, while
either offset binary or two’s complement format may be selected
in the bipolar range. A CLR function is provided which sets the
output to 0 V in both unipolar ranges and in the two’s comple-
ment bipolar range, while with offset binary data format, the
output is set to –REFIN. This function is useful as a power-on
reset as it allows the output to be set to a known voltage level.
The AD7243 features a fast versatile serial interface which
allows easy connection to both microcomputers and 16-bit digi-
tal signal processors with serial ports. The serial data may be
applied at rates up to 5 MHz allowing a DAC update rate of
300 kHz. A serial data output capability is also provided which
allows daisy chaining in multi-DAC systems. This feature allows
any number of DACs to be used in a system with a simple
4-wire interface. All DACs may be updated simultaneously
using LDAC.
FUNCTIONAL BLOCK DIAGRAM
VDD
REFOUT
2R
REFIN
2R
AD7243
12 - BIT DAC
12
DAC LATCH
12
INPUT SHIFT REGISTER
R OFS
VOUT
AGND
DGND
VSS
SDIN CLR BIN/ SCLK SYNC LDAC DCEN SDO
COMP
The AD7243 is fabricated on Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process. It is pack-
aged in 16-lead DIP and 16-lead SOIC packages.
PRODUCT HIGHLIGHTS
1. Complete 12-Bit DACPORT®
The AD7243 is a complete, voltage output, 12-bit DAC on
a single chip. The single chip design is inherently more
reliable than multichip designs.
2. Single or Dual Supply Operation.
3. Minimum 3-wire interface to most DSP processors.
4. DAC Update Rate–300 kHz.
5. Serial Data Output allows easy daisy-chaining in multiple
DAC systems.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD7243
TERMINOLOGY (Continued)
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the out-
put voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7243 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error
Unipolar Offset Error is the measured output voltage from
VOUT with all zeros loaded into the DAC latch when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
PIN CONFIGURATION
DIP and SOIC
REFIN 1
REFOUT 2
CLR 3
BIN/COMP 4
SCLK 5
SDIN 6
SYNC 7
DGND 8
AD7243
16 VDD
15 VSS
14 VOUT
TOP VIEW
(Not to Scale)
13 ROFS
12 AGND
11 SDO
10 DCEN
9 LDAC
CIRCUIT INFORMATION
D/A Section
The AD7243 contains a 12-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The output voltage
from the converter has the same polarity as the reference volt-
age, REFIN, allowing single supply operation.
R OFS
2R
2R
RR
RR
R
VOUT
2R 2R 2R
DB0 DB1
2R
DB9
2R
DB10
2R
DB11
REFIN*
AGND
*BUFFERED REFIN VOLTAGE
SHOWN FOR ALL 1S
ON DAC
Figure 2. D/A Simplified Circuit Diagram
Internal Reference
The AD7243 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 5 V ± 50 mV. The
reference voltage is provided at the REFOUT pin. This refer-
ence can be used to provide the reference voltage for the D/A
converter (by connecting the REFOUT pin to the REFIN pin.)
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500 µA to an ex-
ternal load. The maximum recommended capacitance on
REFOUT for normal operation is 50 pF. If the reference is re-
quired for external use with capacitive loads greater than 50 pF
then it should be decoupled to AGND with a 200 Ω resistor in
series with a parallel combination of a 10 µF tantalum capacitor
and a 0.1 µF ceramic capacitor.
REFOUT
200⍀
10F
0.1F
EXT
LOAD
Figure 3. Reference Decoupling Scheme
External Reference
In some applications, the user may require a system reference or
some other external reference to drive the AD7243. References
such as the AD586 provide an ideal external reference source
(see Figure 10). The REFIN voltage is internally buffered by a
unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the typical
degradation in linearity vs. REFIN.
1.0
0.9 VDD = +15V
VSS = –15V
0.8 TA = +25؇C
0.7
0.6
0.5
0.4
INL
0.3
0.2
DNL
0.1
0.0
2 34 5 6 7
REFIN – Volts
89
Figure 4. Typical Linearity vs. REFIN Voltage
Op Amp Section
The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The ROFS input allows three out-
put voltage ranges to be selected. The buffer amplifier is capable
of developing +10 V across a 2 kΩ load to AGND.
The output amplifier can be operated from a single +12 V to
+15 V supply by tying VSS = 0 V.
The amplifier can also be operated from dual supplies to allow
an additional bipolar output range of –5 V to +5 V. Dual supplies are
necessary for the bipolar output range but can also be used for
the unipolar ranges to give faster settling time to voltages near
REV. A
–5–
5 Page 
Common clock, data, and synchronization signals are applied to
all DACs in the chain. The loading sequence starts by taking
SYNC low. The data is then clocked into the input registers on
the falling edge of SCLK. Sixteen clock pulses are required for
each DAC in the chain. The data ripples through the input reg-
isters with the first 16-bit word filling the last register in the
chain after 16N clock pulses where N = the total number of
DACs in the chain.
When valid data has been loaded into all the registers, the
SYNC input should be taken high and a common LDAC pulse
used to update all the DACs simultaneously.
APPLICATIONS
OPTO-ISOLATED INTERFACE
In many process control type applications it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7243
makes it ideal for opto-isolated interfaces as the number of in-
terface lines is kept to a minimum.
VDD
AD7243
Figure 17 shows a 4-channel isolated interface using the
AD7243. The DCEN pin must be connected high to enable the
daisy-chain facility. Four channels with 12-bit resolution are
provided in the circuit shown, but this may be expanded to ac-
commodate any number of DAC channels without any extra
isolation circuitry.
The sequence of events to program the output channels is as
follows:
1. Take the SYNC line low.
2. Transmit the data as four 16-bit words. A total of 64 clock
pulses is required to clock the data through the chain.
3. Take the SYNC line high.
4. Pulse the LDAC line low. This updates all output channels
simultaneously on the falling edge of LDAC.
To reduce the number of opto-couplers, the LDAC line could
be driven from a one shot which is triggered by the rising edge
on the SYNC line. A low level pulse of 50 ns duration or greater
is all that is required to update the outputs.
DATA OUT
CONTROLLER
CLOCK OUT
SYNC OUT
CONTROL OUT
VDD
VDD
VDD
QUAD OPTO-COUPLER
SDIN
AD7243*
SCLK
SYNC
VOUT
VDD
LDAC DCEN
SDO
VOUT(A)
SDIN
AD7243*
SCLK
SYNC
VOUT
VDD VOUT(B)
LDAC DCEN
SDO
SDIN
AD7243*
SCLK
SYNC
VOUT
VDD VOUT(C)
LDAC DCEN
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
SDIN
AD7243*
SCLK
SYNC
VOUT
VDD VOUT(D)
LDAC DCEN
SDO
Figure 17. Four-Channel Opto-lsolated Interface
REV. A
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7243.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD724 | RGB to NTSC/PAL Encoder | Analog Devices |
| AD7242 | LC2MOS Dual/ Complete/ 12-Bit/14-Bit Serial DACs | Analog Devices |
| AD7243 | LC2MOS 12-Bit Serial DACPORT | Analog Devices |
| AD7244 | LC2MOS Dual/ Complete/ 12-Bit/14-Bit Serial DACs | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |