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PDF AD7249 Data sheet ( Hoja de datos )
| Número de pieza | AD7249 | |
| Descripción | LC2MOS Dual 12-Bit Serial DACPORT | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
LC2MOS
Dual 12-Bit Serial DACPORT®
AD7249
FEATURES
Two 12-Bit CMOS DAC Channels with
On-Chip Voltage Reference
Output Amplifiers
Three Selectable Output Ranges per Channel
–5 V to +5 V, 0 V to +5 V, 0 V to +10 V
Serial Interface
125 kHz DAC Update Rate
Small Size: 16-Lead DIP or SOIC
Low Power Dissipation
APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
GENERAL DESCRIPTION
The AD7249 DACPORT contains a pair of 12-bit, voltage-
output, digital-to-analog converters with output amplifiers and
Zener voltage reference on a monolithic CMOS chip. No exter-
nal trims are required to achieve full specified performance.
The output amplifiers are capable of developing +10 V across a
2 kΩ load. The output voltage ranges with single supply opera-
tion are 0 V to +5 V or 0 V to +10 V, while an additional bipolar
± 5 V output range is available with dual supplies. The ranges
are selected using the internal gain resistor.
Interfacing to the AD7249 is serial, minimizing pin count and
allowing a small package size. Standard control signals allow
interfacing to most DSP processors and microcontrollers. The
data stream consists of 16 bits, DB15 to DB13 are don’t care
bits, the 13th bit (DB12) is used as the channel select bit and
the remaining 12 bits (DB11 to DB0) contain the data to update
the DAC. The 16-bit data word is clocked into the input register
on each falling SCLK edge.
The data format is natural binary in both unipolar ranges, while
either offset binary or twos complement format may be selected
in the bipolar range. A CLR function is provided which sets the
output to 0 V in both unipolar ranges and in the twos comple-
ment bipolar range, while with offset binary data format, the
output is set to –REFIN. This function is useful as a power-on
reset as it allows the outputs to be set to a known voltage level.
REFOUT
FUNCTIONAL BLOCK DIAGRAM
VDD
VSS
AD7249
2R
2R
ROFSA
REFIN
AGND
DGND
12-BIT
DAC A
A1
2R
2R
12-BIT
DAC B
A2
INPUT SHIFT REGISTER
VOUTA
ROFSB
VOUTB
SCLK SDIN SYNC BIN/COMP CLR LDAC
The AD7249 features a serial interface which allows easy con-
nection to both microcomputers and 16-bit digital signal proces-
sors with serial ports. The serial data may be applied at rates up
to 2 MHz allowing a DAC update rate of 125 kHz.
The AD7249 is fabricated on linear compatible CMOS
(LC2MOS), an advanced, mixed technology process. It is pack-
aged in 16-lead DIP and 16-lead SOIC packages.
PRODUCT HIGHLIGHTS
1. Two complete 12-bit DACPORTs
The AD7249 contains two complete voltage output, 12-bit
DACs in both 16-lead DIP and SOIC packages.
2. Single or dual supply operation
3. Minimum 3-wire interface to most DSP processors
4. DAC update rate—125 kHz
DACPORT is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD7249
TERMINOLOGY
Bipolar Zero Error
Bipolar Zero Error is the voltage measured at VOUT when the
DAC is configured for bipolar output and loaded with all 0s
(Twos Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Full-Scale Error
Full-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at VOUT when the digital
code in the DAC Latch changes, before the output settles to its
final value. It is normally specified as the area of the glitch in
nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (0111 1111 1111 to 1000
0000 0000 or 1000 0000 0000 to 0111 1111 1111).
Digital Feedthrough
This is a measure of the voltage spike that appears on VOUT as a
result of feedthrough from the digital inputs on the AD7249. It
is measured with LDAC held high.
Relative Accuracy (Linearity)
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Single Supply Linearity and Gain Error
The output amplifier on the AD7249 can have true negative
offsets even when the part is operated from a single +15 V sup-
ply. However, because the negative supply rail (VSS) is 0 V, the
output cannot actually go negative. Instead, when the output
offset voltage is negative, the output voltage sits at 0 V, resulting
in the transfer function shown in Figure 1.
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the
output voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7249 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions, the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error
Unipolar Offset Error is the measured output voltage from VOUT
with all zeros loaded into the DAC latch, when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
CIRCUIT INFORMATION
D/A Section
The AD7249 contains two 12-bit voltage-mode D/A converters
consisting of highly stable thin film resistors and high-speed
NMOS single-pole, double-throw switches. The simplified
circuit diagram for the DAC section is shown in Figure 2. The
output voltage from the converter has the same polarity as the
reference voltage, REFIN, allowing single supply operation.
ROFS
2R
2R
R RRRR
VOUT
2R 2R 2R
2R 2R 2R
OUTPUT
VOLTAGE
REFIN*
AGND
SHOWN FOR ALL 1s
ON DAC
*BUFFERED REFIN VOLTAGE
Figure 2. D/A Simplified Circuit Diagram
0V
NEGATIVE
OFFSET
DAC CODE
Figure 1. Effect of Negative Offset (Single Supply)
REV. C
–5–
5 Page 
AD7249–68HC11 Interface
Figure 14 shows a serial interface between the AD7249 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7249 while the MOSI output drives the serial data line
of the AD7249. The SYNC signal is derived from a port line
(PC0 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a
1. When data is to be transmitted to the part, PC0 is taken low.
When the 68HC11 is configured like this, data on MOSI is
valid on the falling edge of SCK. The 68HC11 transmits its
serial data in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. To load data to the AD7249,
PC0 is left low after the first eight bits are transferred and a sec-
ond byte of data is then transferred serially to the AD7249.
When the second serial transfer is complete, the PC0 line is
taken high.
Figure 14 shows the LDAC input of the AD7249 being driven
from another bit programmable port line (PC1). As a result,
both DACs can be updated simultaneously by taking LDAC
low after both DACs latches have updated.
68HC11*
PC1
PC0
SCK
MOSI
AD7249*
LDAC
SYNC
SCLK
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 14. AD7249–68HC11 Interface
AD7249–87C51 Interface
A serial interface between the AD7249 and the 87C51 micro-
controller is shown in Figure 15. TXD of the 87C51 drives
SCLK of the AD7249 while RXD drives the serial data line of
the part. The SYNC signal is derived from the port line P3.3
and the LDAC line is driven port line P3.2.
The 87C51 provides the LSB of its SBUF register as the first
bit in the serial data stream. Therefore, the user will have to
ensure that the data in the SBUF register is arranged correctly
so that the don’t care bits are the first to be transmitted to the
AD7249 and the last bit to be sent is the LSB of the word to be
loaded to the AD7249. When data is to be transmitted to the
part, P3.3 is taken low. Data on RXD is valid on the falling
edge of TXD. The 87C51 transmits its serial data in 8-bit bytes
with only eight falling clock edges occurring in the transmit
cycle. To load data to the AD7249, P3.3 is left low after the
first eight bits are transferred, and a second byte of data is then
transferred serially to the AD7249 with DB12 used to select
the appropriate DAC register. When the second serial transfer
is complete, the P3.3 line is taken high and then taken low
again to start the loading sequence to the second DAC (see
timing diagram Figure 8).
AD7249
Figure 15 shows the LDAC input of the AD7249 driven from
the bit programmable port line P3.2. As a result, both DAC
outputs can be updated simultaneously by taking the LDAC
line low following the completion of the write cycle to the sec-
ond DAC. Alternatively LDAC could be hardwired low and the
analog output will be updated on the sixteenth falling edge of
TXD after the SYNC signal for the DAC has gone low.
87C51*
P3.2
P3.3
TXD
RXD
AD7249*
LDAC
SYNC
SCLK
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 15. AD7249–87C51 Interface
APPLICATIONS
OPTO-ISOLATED INTERFACE
In many process control type applications it is necessary to
provide an isolation barrier between the controller and the
unit being controlled. Opto-isolators can provide voltage
isolation in excess of 3 kΩ. The serial loading structure of the
AD7249 makes it ideal for opto-isolated interfaces as the num-
ber of interface lines is kept to a minimum.
Figure 16 shows a 2-channel isolated interface using the
AD7249.
The sequence of events to program the output channels is as
follows.
1. Take the SYNC line low.
2. Transmit the 16-bit word for DAC A (DB 12 of the 16-bit
data word selects the DAC, DB12 = 0 to select DAC A) and
bring the SYNC line high after the 16 bits have been trans-
mitted.
3. Bring SYNC line low again and transmit 16 bits for DAC B,
bring SYNC back high at end of transmission.
4. Pulse the LDAC line low. This updates both output chan-
nels simultaneously on the falling edge of LDAC.
REV. C
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7249.PDF ] | |
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