Datasheet.kr   

AD7265 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7265은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AD7265 자료 제공

부품번호 AD7265 기능
기능 Differential Input/ Dual 1 MSPS/ 12-Bit/ 3-Channel SAR ADC
제조업체 Analog Devices
로고 Analog Devices 로고


AD7265 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 16 페이지수

미리보기를 사용할 수 없습니다

AD7265 데이터시트, 핀배열, 회로
Preliminary Technical Data
FEATURES
Dual 12-bit, 3-channel ADC
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power: 7 mW max at 1 MSPS with 3 V supplies
16.5 mW max at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
On-chip reference: 2.5 V
–40°C to +125°C operation
Flexible power/throughput rate management
Simultaneous conversion/read
No pipeline delays
High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 1 µA max
32-lead LFCSP and TQFP packages
GENERAL DESCRIPTION
The AD7265 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a 3-channel multi-
plexer, and a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 10 MHz.
The conversion process and data acquisition are controlled using
standard control inputs, allowing easy interfacing to microproces-
sors or DSPs. The input signal is sampled on the falling edge of CS;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined delays
associated with the part.
The AD7265 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 5 V supplies and a
1 MSPS throughput rate, the part consumes ? mA maximum. The
part also offers flexible power/throughput rate management when
operating in sleep mode.
The analog input range for the part can be selected to be a 0 V to
VREF range or a 2VREF range with either straight binary or twos
complement output coding. The AD7265 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre-
ferred. This external reference range is 100 mV to 2.5 V. The
AD7265 is available in 32-lead lead frame chip scale (LFCSP) and
thin flat quad (TQFP) lead package.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Differential Input, Dual 1 MSPS,
12-Bit, 3-Channel SAR ADC
AD7265
VA1
VA2
VA3
VA4
VA5
VA6
VB1
V
B2
VB3
VB4
VB5
VB6
FUNCTIONAL BLOCK DIAGRAM
REF SELECT
DcapA
AVdd DVdd
REF
BUF
MUX
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AD7265
OUTPUT
DRIVERS
CONTROL
LOGIC
12-BIT
T/H SUCCESSIVE
APPROXIMATION
MUX
ADC
OUTPUT
DRIVERS
DOUTA
SCLK
+5
RANGE
DIFF/SE
A0
A1
A2
VDRIVE
DOUTB
BUF
AGND AGND AGND DcapB
DGND
DGND
Figure 1
PRODUCT HIGHLIGHTS
1. The AD7265 features two complete ADC functions that allow
simultaneous sampling and conversion of two channels. Each
ADC has 2 analog inputs, 3 fully differential pairs, or 6 single-
ended channels as programmed. The conversion result of both
channels is available simultaneously on separate data lines, or
in succession on one data line if only one serial port is
available.
2. High Throughput with Low Power Consumption
The AD7265 offers a 1 MSPS throughput rate with ? mW
maximum power consumption when operating at 3 V.
3. Flexible Power/Throughput Rate Management
The conversion rate is determined by the serial clock, allowing
power consumption to be reduced as conversion time is re-
duced through an SCLK frequency increase. Power efficiency
can be maximized at lower throughput rates if the part enters
sleep between conversions.
4. No Pipeline Delay
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a CS
input and once off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




AD7265 pdf, 반도체, 판매, 대치품
AD7265
Preliminary Technical Data
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time3
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD6
Normal Mode (Static)
Operational, fs = 1 MSPS
Partial Power-Down Mode
Partial Power-Down Mode
Full Power-Down Mode
Power Dissipation6
Normal Mode (Operational)
Partial Power-Down (Static)
Full Power-Down (Static)
Specification Unit
Test Conditions/Comments
VDRIVE – 0.2
0.4
V min
V max
±1 µA max
10 pF max
Straight (Natural) Binary
Twos Complement
SGL/DIFF = 1 with 0 V to VREF range selected
SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range
14 SCLK Cycles TBD ns with SCLK = 16 MHz
100 ns max
TBD MSPS max
2.7/5.25
2.7/5.25
TBD
3.3
2.3
TBD
TBD
TBD
V min/V max
V min/V max
mA max
mA max
mA max
mA max
µA max
µA max
Digital I/Ps = 0 V or VDRIVE
VDD = 5 V
VDD = 3 V
fs = 200 kSPS
Static
16.5
mW max
VDD = 5 V
TBD mW max
TBD mW max
NOTES
1 Temperature ranges as follows: -40°C to +125°C
2 See Terminology section.
3 Sample tested during initial release to ensure compliance.
4 Relates to Pins DCAPA or DCAPB.
5 See Reference section for DCAPA, DCAPB output impedances.
6 See Power Versus Throughput Rate section.
TIMING SPECIFICATIONS
Table 2. AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, TA = TMAX to TMIN, unless otherwise noted
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
10
kHz min
20 MHz max
tCONVERT
14 × tSCLK
ns max
tSCLK = 1/fSCLK
700
ns max
fSCLK = 20 MHz,
tQUIET
35
ns max
Minimum time between end of serial read and next falling edge of CS
t2 10
ns min
CS to SCLK setup time
t3 TBD
ns max
Delay from CS until DOUTA and DOUTB are three-state disabled
t4 TBD
ns max
Data access time after SCLK falling edge.
t5 0.4tSCLK
ns min
SCLK low pulse width
t6 0.4tSCLK
ns min
SCLK high pulse width
t7 TBD
ns min
SCLK to data valid hold time
t8 25
ns max
CS rising edge to DOUTA, DOUTB, high impedance
t9 TBD
ns min
SCLK falling edge to DOUTA, DOUTB, high impedance
TBD
ns max
SCLK falling edge to DOUTA, DOUTB, high impedance
Rev. PrA | Page 4 of 16

4페이지










AD7265 전자부품, 판매, 대치품
Preliminary Technical Data
AD7265
Pin No.
21
25–23
22
2
Mnemonic
RANGE
A0–A2
SGL/DIFF
REF SELECT
Description
Analog Input Range Selection. Logic input. The polarity on this pin will determine what input range the analog
input channels will have. On the falling edge of CS , the polarity of this pin is checked to determine the analog
input range of the next conversion. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin
is tied to a logic high when CS goes low, the analog input range is 2 × VREF.
Multiplexer Select. Logic inputs. Thess inputs are used to select the pair of channels to be converted
simultaneously, i.e., Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC, and so on. The pair of
channels selected may be two single ended channels or two differential pairs. The logic states of these pins are
checked upon the falling edge of CS, and the multiplexer is set up for the next conversion. See Table 6 for
multiplexer address decoding.
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic
low selects differential operation while a logic high selects single ended operation.
Internal/External reference Selection. Logic Input. If this pin is tied to GND, the on-chip 2.5 V reference is used as
the reference source for both ADC A and ADC B. In addition, Pins DCAPA and DCAPB must be tied to decoupling
capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7265
through the DCAPA and/or DCAPB pins.
Rev. PrA | Page 7 of 16

7페이지


구       성 총 16 페이지수
다운로드[ AD7265.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
AD7262

Simultaneous Sampling SAR ADC

Analog Devices
Analog Devices
AD7264

Simultaneous Sampling SAR ADC

Analog Devices
Analog Devices

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵