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PDF AD73322L Data sheet ( Hoja de datos )
| Número de pieza | AD73322L | |
| Descripción | Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a Low Cost, Low Power CMOS
General-Purpose Dual Analog Front End
AD73322L
FEATURES
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
78 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows Up to Four Dual
Codecs to be Connected in Cascade Giving Eight
I/O Channels
Single (2.7 V to 3.3 V) Supply Operation
50 mW Typ Power Consumption at 3.0 V
Temperature Range: –40؇C to +105؇C
On-Chip Reference
28-Lead SOIC, TSSOP, and 44-Lead LQFP Packages
APPLICATIONS
General-Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
Wireless Local Loop
VFBP1
VINP1
VINN1
VFBN1
VOUTP1
VOUTN1
REFOUT
REFCAP
VFBP2
VINP2
VINN2
VFBN2
VOUTP2
VOUTN2
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2
DVDD
AD73322L
ADC CHANNEL 1
SDI
SDIFS
DAC CHANNEL 1
REFERENCE
SPORT
SCLK
SE
RESET
ADC CHANNEL 2
MCLK
DAC CHANNEL 2
SDOFS
SDO
AGND1 AGND2 DGND
GENERAL DESCRIPTION
The AD73322L is a dual front-end processor for general pur-
pose applications including speech and telephony. It features
two 16-bit A/D conversion channels and two 16-bit D/A con-
version channels. Each channel provides 78 dB signal-to-noise
ratio over a voiceband signal bandwidth. It also features an
input-to-output gain network in both the analog and digital
domains. This is featured on both codecs and can be used for
impedance matching or scaling when interfacing to Subscriber
Line Interface Circuits (SLICs).
The AD73322L is particularly suitable for a variety of applica-
tions in the speech and telephony area, including low bit rate,
high quality compression, speech enhancement, recognition and
synthesis. The low group delay characteristic of the part makes
it suitable for single or multichannel active control applications.
The A/D and D/A conversion channels feature programmable
input/output gains with ranges 38 dB and 21 dB respectively.
An on-chip reference voltage is included to allow single-
supply operation.
The sampling rate of the codecs is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73322L is available in 28-lead SOIC, 28-lead TSSOP,
and 44-lead LQFP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
AD73322L
VREFCAP
VREFOUT
ADC
DAC
Table II. Signal Ranges
Maximum Input Range at VIN
Nominal Reference Level
Maximum Voltage Output Swing
Single-Ended
Differential
Nominal Voltage Output Swing
Single-Ended
Differential
Output Bias Voltage
3 V Power Supply
5VEN = 0
1.2 V ± 10%
1.2 V ± 10%
1.578 V p-p
1.0954 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
VREFOUT
TIMING CHARACTERISTICS (AVDD = 3 V ؎ 10%; DVDD = 3 V ؎ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted.)
Parameter
Limit at
TA = –40؇C to +105؇C
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
Specifications subject to change without notice.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
REV. 0
–5–
5 Page 
AD73322L
FUNCTIONAL DESCRIPTION
Encoder Channels
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part of
the sigma-delta ADC, also performs critical system-level filtering.
Due to the high level of oversampling, the input antialias require-
ments are reduced such that a simple single pole RC stage is
sufficient to give adequate attenuation in the band of interest.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta modula-
tor. The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table III, may be used
to increase the signal level applied to the ADC from low output
sources such as microphones, and can be used to avoid placing
external amplifiers in the circuit. The input signal level to the
sigma-delta modulator should not exceed the maximum input
voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
interest to an out-of-band position (Figure 7b). The combina-
tion of these techniques, followed by the application of a digital
filter, sufficiently reduces the noise in band to ensure good
dynamic performance from the part (Figure 7c).
BAND
OF
INTEREST
a.
NOISE SHAPING
BAND
OF
INTEREST
b.
FS/2
DMCLK/16
FS/2
DMCLK/16
Table III. PGA Settings for the Encoder Channel
IGS2
0
0
0
0
1
1
1
1
IGS1
0
0
1
1
0
0
1
1
IGS0
0
1
0
1
0
1
0
1
Gain (dB)
0
6
12
18
20
26
32
38
ADC
Both ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decimation
filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta Modulator
The AD73322L’s input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73322L, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to FS/2 = DMCLK/16
(Figure 7a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
DIGITAL FILTER
BAND
OF
INTEREST
c.
FS/2
DMCLK/16
Figure 6. Sigma-Delta Noise Reduction
Figure 7 shows the various stages of filtering that are employed
in a typical AD73322L application. In Figure 7a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling fre-
quency. This also shows the major difference between the initial
oversampling rate and the bandwidth of interest. In Figure 7b,
the signal and noise-shaping responses of the sigma-delta modu-
lator are shown. The signal response provides further rejection
of any high frequency signals while the noise-shaping will push
the inherent quantization noise to an out-of-band position. The
detail of Figure 7c shows the response of the digital decimation
filter (Sinc-cubed response) with nulls every multiple of DMCLK/
256, which corresponds to the decimation filter update rate
for a 64 kHz sampling. The nulls of the Sinc3 response corre-
spond with multiples of the chosen sampling frequency. The
final detail in Figure 7d shows the application of a final anti-
alias filter in the DSP engine. This has the advantage of being
implemented according to the user’s requirements and available
MIPS. The filtering in Figures 7a through 7c is implemented in
the AD73322L.
REV. 0
–11–
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