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PDF AD73460 Data sheet ( Hoja de datos )
| Número de pieza | AD73460 | |
| Descripción | Six-Input Channel Analog Front End | |
| Fabricantes | Analog Devices | |
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FEATURES
AFE PERFORMANCE
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
72 dB SNR
64 kS/s Maximum Sample Rate
–80 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel)
Programmable Input Gain
Single Supply Operation
On-Chip Reference
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
Six-Input Channel
Analog Front End
AD73460
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
AD73460
MEMORY
16K PM 16K DM
(OPTIONAL (OPTIONAL
8K) 8K)
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
ADSP-2100 BASE
ARCHITECTURE
REF
SERIAL PORT
SPORT 2
ADC1 ADC2 ADC3 ADC4 ADC5 ADC6
ANALOG FRONT END
SECTION
GENERAL DESCRIPTION
The AD73460 is a six-input channel analog front-end processor
for general-purpose applications including industrial power meter-
ing or multichannel analog inputs. It features six 16-bit A/D
conversion channels, each of which provides 72 dB signal-to-noise
ratio over a dc-to-2 kHz signal bandwidth. Each channel also
features a programmable input gain amplifier (PGA) with gain
settings in eight stages from 0 dB to 38 dB.
The AD73460 is particularly suitable for industrial power metering
as each channel samples synchronously, ensuring that there is
no (phase) delay between the conversions. The AD73460 also
features low group delay conversions on all channels.
An on-chip reference voltage of 1.25 V is included. The sampling
rate of the device is programmable with separate settings
offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of input channels by cas-
cading an extra AFE external to the AD73460.
The AD73460’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
The AD73460-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM and 16K
(16-bit) of data RAM. The AD73460-40 integrates 40K bytes
of on-chip memory configured as 8K words (24-bit) of program
RAM and 8K (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery-operated
portable equipment. The AD73460 is available in a 119-ball
PBGA package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
AD73460
SPECIFICATIONS (AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSAMP = 64 kHz;
TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Test Conditions
Min Typ Max Unit
DSP SECTION
VIH Hi-Level Input Voltage1, 2
@ VDD = max
2.0 V
VIH Hi-Level CLKIN Voltage
@ VDD = max
2.2 V
VIL Lo-Level Input Voltage1, 3
VOH Hi-Level Output Voltage1, 4, 5
@ VDD = min
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA6
2.4
VDD–0.3
0.8 V
V
V
VOL Lo-Level Output Voltage1, 4, 5
IIH Hi-Level Input Current3
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
0.4 V
10 µA
IIL Lo-Level Input Current3
IOZH Three-State Leakage Current7
IOZL Three-State Leakage Current7
IDD Supply Current (Idle)9
IDD Supply Current (Dynamic)11
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max8
@ VDD = max, VIN = 0 V8
@ VDD = 3.3 V
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VDD = 3.3 V, TAMB = 25°C
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
10
10
10
14
12
10
54
43
37
µA
µA
µA
mA
mA
mA
mA
mA
mA
CI Input Pin Capacitance3, 6, 12
CO Output Pin Capacitance6, 7, 12, 13
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
8 pF
8 pF
NOTES
1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2Input only pins: RESET, BR, DR0, DR1, PWD.
3Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5Although specified for TTL outputs, all AD73460 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6Guaranteed but not tested.
7Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
80 V on BR.
9Idle refers to AD73460 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.
12Applies to PBGA package type.
13Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
REV. 0
–5–
5 Page 
AD73460
VINP1
VINN1
VINP2
VINN2
SIGNAL
CONDITIONING
0/38dB
PGA
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
DECIMATOR
VINP3
VINN3
REFCAP
REFOUT
VINP4
VINN4
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
REFERENCE
AFE SECTION
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
VINP5
VINN5
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
VINP6
VINN6
SIGNAL
CONDITIONING
0/38dB
PGA
ANALOG
⌺-⌬
MODULATOR
DECIMATOR
AD73460
SDI
SDIFS
SCLK2
SERIAL
I/O
PORT
ARESET
AMCLK
SE
SDO
SDOFS
Figure 2. Functional Block Diagram of Analog Front End
FUNCTIONAL DESCRIPTION—AFE
Encoder Channel
Each encoder channel consists of a signal conditioner, a switched
capacitor PGA, and a sigma-delta analog-to-digital converter
(ADC). An on-board digital filter, which forms part of the
sigma-delta ADC, also performs critical system-level filtering.
Due to the high level of oversampling, the input antialias require-
ments are reduced such that a simple single pole RC stage is
sufficient to give adequate attenuation in the band of interest.
Signal Conditioner
Each analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a Switched
Capacitor PGA that also forms part of the sigma-delta modulator.
The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table II, may be used
to increase the signal level applied to the ADC from low output
sources such as microphones, and can be used to avoid placing
external amplifiers in the circuit. The input signal level to the
sigma-delta modulator should not exceed the maximum input
voltage permitted.
The PGA gain is set by bits IGS0, IGS1, and IGS2 in control
Registers D, E, and F.
Table II. PGA Settings for the Encoder Channel
IxGS2
0
0
0
0
1
1
1
1
IxGS1
0
0
1
1
0
0
1
1
IxGS0
0
1
0
1
0
1
0
1
Gain (dB)
0
6
12
18
20
26
32
38
ADC
Each channel has its own ADC consisting of an analog sigma-
delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and increases
the resolution.
REV. 0
–11–
11 Page | ||
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