PDF AD7376 Data sheet ( Hoja de datos )

Número de pieza	AD7376
Descripción	+-15 V Operation Digital Potentiometer
Fabricantes	Analog Devices
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No Preview Available ! a ؎15 V Operation Digital Potentiometer AD7376* FEATURES 128 Position Potentiometer Replacement 10 k⍀, 50 k⍀, 100 k⍀, 1 M⍀ Power Shutdown: Less than 1 ␮A 3-Wire SPI Compatible Serial Data Input +5 V to +30 V Single Supply Operation ؎5 V to ؎15 V Dual Supply Operation Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment GENERAL DESCRIPTION The AD7376 provides a single channel, 128-position digitally- controlled variable resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or vari- able resistor. These products were optimized for instrument and test equipment applications where a combination of high voltage with a choice between bandwidth or power dissipation are avail- able as a result of the wide selection of end-to-end terminal resis- tance values. The AD7376 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input regis- ter. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code trans- ferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 10 kΩ, 50 kΩ, 100 kΩ or 1 MΩ has a nominal tem- perature coefficient of –300 ppm/°C. The VR has its own VR latch which holds its programmed resis- tance value. The VR latch is updated from an internal serial-to- parallel shift register which is loaded from a standard 3-wire serial-input digital interface. Seven data bits make up the data word clocked into the serial data input register (SDI). Only the last seven bits of the data word loaded are transferred into the 7-bit VR latch when the CS strobe is returned to logic high. A serial data output pin (SDO) at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic. The reset (RS) pin forces the wiper to the midscale position by loading 40H into the VR latch. The SHDN pin forces the resistor *Patent Number: 5495245 FUNCTIONAL BLOCK DIAGRAM SDO SDI CLK CS AD7376 Q 7-BIT SERIAL REGISTER D CK 7 7-BIT 7 LATCH R SHDN VDD A W B VSS GND RS SHDN to an end-to-end open circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When shutdown is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown as long as power to VDD is not re- moved. The digital interface is still active in shutdown so that code changes can be made that will produce a new wiper posi- tion when the device is taken out of shutdown. The AD7376 is available in both surface mount (SOL-16) and the 14-lead plastic DIP package. For ultracompact solutions selected models are available in the thin TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C. For operation at lower supply voltages (+3 V to +5 V), see the AD8400/AD8402/ AD8403 products. SDI 1 (DATA IN) 0 SDO 1 (DATA OUT) 0 1 CLK 0 t CSH0 1 CS 0 VDD VOUT 0V DX D'X DX t DS t DH D'X t CH t CSS t CL t CSH tPD_MAX t CS1 t CSW tS ؎1 LSB ERROR BAND Figure 1. Detail Timing Diagram ؎1 LSB The last seven data bits clocked into the serial input register will be transferred to the VR 7-bit latch when CS returns to logic high. Extra data bits are ignored. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997 1 page 0.25 0.20 0.15 0.10 0.05 TA = +25؇C TA = –55؇C 0 –0.05 –0.10 –0.15 –0.20 VDD = +15V VSS = –15V VA = +2.5V VB = 0V RAB = 50k⍀ TA = +85؇C –0.25 0 16 32 48 64 80 96 112 128 CODE – Decimal Figure 11. Potentiometer Divider Nonlinearity Error vs. Code 0.25 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 VDD = +15V VSS = –15V VA = +2.5V VB = 0V RAB = 50k⍀ –0.25 0 16 32 48 64 80 96 112 128 CODE – Decimal Figure 12. Potentiometer Divider Differential Nonlinearity Error vs. Code AD7376 40 35 VDD = +15V 30 VSS = –15V RAB = 50k⍀ 25 20 15 10 5 0 –5 –10 0 16 32 48 64 80 96 112 128 CODE – Decimal Figure 13. ∆RWB/∆T Rheostat Mode Tempco CODE = 7FH RAB = 10k⍀ 0 CODE = 40H –6 CODE = 20H –12 CODE = 10H –18 CODE = 08H –24 CODE = 04H –30 CODE = 02H –36 CODE = 01H –42 CODE = 00H –48 A W VDD = +15V VSS = –15V B OP275 VAMPL = 50mVrms 1k 10k 100k 1M FREQUENCY – Hz Figure 14. 10 kΩ Gain vs. Frequency vs. Code 0 –6 –12 –18 –24 –30 –36 –42 A –48 B 100 CODE = 7FH RAB = 1M⍀ CODE = 40H CODE = 20H CODE = 10H CODE = 08H CODE = 04H CODE = 02H CODE = 01H W OP275 VDD = +15V VSS = –15V VAMPL = 50mVrms RAB = 1M⍀ 1k 10k FREQUENCY – Hz 100k Figure 15. 1 MΩ Gain vs. Frequency vs. Code 259.8␮s VDD = +15V VSS = —15V CODE = 3FH 40H 3FH VA = 2.5V VB = 0V f = 100 kHz 50m B Lw HO5␮s 5␮S/DIV Figure 16. Midscale Transition Glitch 0 CODE = 7FH RAB = 50k⍀ CODE = 40H 128kHz –6 20H –12 10H –18 –24 AMP = 50mV –30 VDD = +15V VSS = –15V 08H 04H 02H –36 RL = 1M⍀ 01H –42 A –48 B –54 1k OP275 10k 100k 1M FREQUENCY – Hz Figure 17. 50 kΩ Gain vs. Frequency vs. Code A2 1.6 V DLY 27.08␮s 12 CODE = 3FH VA = 12V VDD = +15V VSS = –15V 0 VB = 0V f = 1 MHz 5 0 5V 5V B Lw 2␮S/DIV HO2␮s Figure 18. Large Signal Settling Time 1.0 0.1 0.010 NON-INVERTING MODE TEST CKT FIG 36 VDD = +15V VSS = –15V VA = ؎10V p–p CODE = 40H RAB = 50k⍀ 0.001 0.0005 10 NON-INVERTING MODE TEST CKT FIG 35 100 1k 10k FREQUENCY – Hz 200k Figure 19. Total Harmonic Distortion Plus Noise vs. Frequency REV. 0 –5– 5 Page AD7376 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Plastic DIP (N-14) 14-Lead TSSOP (RU-14) 0.795 (20.19) 0.725 (18.42) 14 8 0.280 (7.11) 1 7 0.240 (6.10) PIN 1 0.060 (1.52) 0.210 (5.33) 0.015 (0.38) MAX 0.130 0.160 (4.06) 0.115 (2.93) (3.30) MIN 0.022 (0.558) 0.014 (0.356) 0.100 0.070 (1.77) SEATING (2.54) 0.045 (1.15) PLANE BSC 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.201 (5.10) 0.193 (4.90) 14 8 1 7 0.006 (0.15) 0.002 (0.05) PIN 1 SEATING PLANE 0.0256 0.0118 (0.30) (0.65) 0.0075 (0.19) BSC 0.0433 (1.10) MAX 8° 0.0079 (0.20) 0° 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 16-Lead Wide Body SOIC (R-16) 0.4133 (10.50) 0.3977 (10.00) 16 9 18 0.0118 (0.30) 0.0040 (0.10) PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45° 0.0098 (0.25) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8° SEATING 0.0125 (0.32) 0° PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) REV. 0 –11– 11 Page

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