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AD7394 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7394은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AD7394 자료 제공

부품번호 AD7394 기능
기능 +3 V/ Dual/ Serial Input 12-/10-Bit DACs
제조업체 Analog Devices
로고 Analog Devices 로고


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AD7394 데이터시트, 핀배열, 회로
a
+3 V, Dual, Serial Input
12-/10-Bit DACs
AD7394/AD7395
FEATURES
Micropower: 100 A/DAC
0.1 A Typical Power Shutdown
Single-Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP-14 Package
AD7394/12-Bit Resolution
AD7395/10-Bit Resolution
Serial Interface with Schmitt Trigger Inputs
APPLICATIONS
Automotive Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
The AD7394/AD7395 family of dual, 12-/10-bit, voltage output
digital-to-analog converters is designed to operate from a single
+3 V supply. Built using a CBCMOS process, this monolithic
DAC offers the user low cost and ease of use in single-supply
+3 V systems. Operation is guaranteed over the supply voltage
range of +2.7 V to +5.5 V making this device ideal for battery
operated applications.
The full-scale output voltage is determined by the applied exter-
nal reference input voltage, VREF. The rail-to-rail VREF input
to VOUT outputs allows for a full-scale voltage set equal to the
positive supply VDD or any value in between.
A doubled-buffered serial data interface offers high speed,
microcontroller compatible inputs using serial-data-in (SDI),
clock (CLK) and load strobe (LDA + LDB) pins. A chip-select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, an RS
input sets the output to zero scale or to 1/2 scale based on the
logic level applied to the MSB pin. The power shutdown pin,
SHDN, reduces power dissipation to nanoamp current levels.
All digital inputs contain Schmitt-triggered logic levels to mini-
mize power dissipation and prevent false triggering on the clock
input.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their application with-
out circuit card redesign.
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
EN
SDI
(DATA)
R
S
H
I
F
T
E
G
I
S
T
E
R
LDA
LDB
VDD VREF
R
D
A
C
E
G
I
S
A
T
E
R
D
PR
12
R
D
D
A
C
E
G
I
S
B
T
E
R
PR
DAC A
OP
AMP A
AD7394/AD7395
DAC B
OP
AMP B
VOUTA
VOUTB
DGND
MSB
RS
AGND
SHDN
The AD7394/AD7395 is specified over the extended industrial
(–40°C to +85°C) temperature range. Packages available in-
clude plastic DIP and low profile 1.75 mm height SO-14 surface
mount packages. The AD7395ARU is available for ultracompact
applications in a thin 1.1 mm TSSOP-14 package. For automotive
applications the AD7395AR is specified for operation over the
(–40°C to +125°C) temperature range.
1
VDD = 3V
0.8 VREF = 2.5V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8 TA = –55؇C, +25؇C, +85؇C
SUPERIMPOSED
–1
0 500 1000 1500 2000 2500
CODE – Decimal
3000
3500
4000
Figure 1. Differential Nonlinearity Error vs. Code
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998




AD7394 pdf, 반도체, 판매, 대치품
AD7394/AD7395
SDI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLK
CS
LDA,B
tCSS
tLD1
tCSH
tLD2
SDI
CLK
LDA,B
RS
FS
VOUT
ZS
tDS tDH
tCL
tCH
tLDW
tS
tCLRW
؎1 LSB
ERROR BAND
Figure 2. Timing Diagram
tS
SHDN
IDD
tSDR
Figure 3. Timing Diagram
CS CLK RS
MSB
SHDN
Table I. Control Logic Truth Table
LDA/B Serial Shift Register Function
DAC Register Function
HX
HX
H
H
No Effect
Latched
LL
HX
H
H
No Effect
Latched
LH H X
H
H
No Effect
Latched
L + H X
H
H
Shift-Register-Data Advanced One Bit Latched
L + H X
H
L
Shift-Register-Data Advanced One Bit Transparent
LH H X
H
L
No Effect
Transparent
+ L
HX
H
H
No Effect
Latched
HX
HX
H
No Effect
Updated with Current Shift Register
Contents
HX
HX
H
L
No Effect
Transparent
XX
XX
XX
LH
+ H
LL
H
H
H
X
H
X
No Effect
No Effect
No Effect
Loaded with 800H
Latched with 800H
Loaded with All Zeros
XX
+ L
H
H
No Effect
Latched All Zeros
XX
XX
L
X
No Effect
No Affect
NOTES
1. + positive logic transition; – negative logic transition; X Don’t Care
2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW.
–4– REV. 0

4페이지










AD7394 전자부품, 판매, 대치품
Typical Performance Characteristics– AD7394/AD7395
1.5
VDD = 3V
TA = –55؇C
VREF = 2.5V
1
0.5
0
–0.5
TA = +25؇C, +85؇C
–1
–1.5
0 500 1000 1500 2000 2500 3000 3500 4000
CODE – Decimal
Figure 4. AD7394 Integral Nonlinear-
ity Error vs. Code
25
SS = 200 UNITS
TA = +25؇C
20 VDD = 2.7V
VREF = 2.5V
15
AD7394
10
5
0
؊3 ؊2 ؊1
0
1
TOTAL UNADJUSTED ERROR – LSB
Figure 5. Total Unadjusted Error
Histogram
50
SS = 200 UNITS
TA = +25؇C
40 VDD = 2.7V
VREF = 2.5V
30
AD7395
20
10
0
–5 0
5 10 15
TOTAL UNAJUSTED ERROR – LSB
Figure 6. Total Unadjusted Error
Histogram
35
AD7395
30
25
SS = 200,
VDD = 2.7V
VREF = 2.5V
TA = +85؇C TO –40؇C
20
15
10
5
0
26
28 30 32 34 36 38
TEMPCO – ppm/؇C
40
Figure 7. Full-Scale Output Tempco
Histogram
0.6
AD7394
0.5
0.4
0.3
VDD = 5.0V
TA = +25؇C
CODE = 768H
0.2
0.1
0
0 0.5 1
1.5 2 2.5 3 3.5
VREF – Volts
4 4.5
5
Figure 8. Integral Nonlinearity Error
vs. VREF
30
AD7394
25
TA = +25؇C
20
15
10 TOTAL UNADJUSTED
FULL SCALE ERROR
5
0
؊5
FULL SCALE ERROR
؊10
؊15
0 0.5
1 1.5 2 2.5 3 3.5 4 4.5
VREF – Volts
5
Figure 9. Full-Scale Error vs. VREF
10
VDD = 5V
VREF = 2.5V
8 TA = +25؇C
6
4
2
0
1 10 100 1k 10k 100k
FREQUENCY – Hz
Figure 10. AD7394 Output Noise
Density vs. Frequency
140
VDD = 3V
135
AD7394
130
125 VIN 3V TO 0V
120
VIN 0V TO 3V
115
110
105
100
0 0.5 1 1.5 2 2.5 3
VIN – Volts
Figure 11. Supply Current vs. Logic
Input Voltage
5
AD7394
4.5
4
3.5 VLOGIC FROM LOW TO HIGH
3
2.5
2
1.5 VLOGIC FROM HIGH TO LOW
1
23 4 56
VDD – Volts
7
Figure 12. Logic Threshold vs. Sup-
ply Voltage
REV. 0
–7–

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