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부품번호 | AD7398 기능 |
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기능 | Quad/ Serial-Input 12-Bit/10-Bit DACs | ||
제조업체 | Analog Devices | ||
로고 | |||
전체 16 페이지수
a
FEATURES
AD7398—12-Bit Resolution
AD7399—10-Bit Resolution
Programmable Power Shutdown
Single (3 V to 5 V) or Dual (؎5 V) Supply Operation
3-Wire Serial SPI-Compatible Interface
Internal Power ON Reset
Double Buffered Registers for Simultaneous
Multichannel DAC Update
Four Separate Rail-to-Rail Reference Inputs
Thin Profile TSSOP-16 Package Available
Low Tempco 1.5 ppm/؇C
APPLICATIONS
Automotive Output Voltage Span
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage-
output digital-to-analog converters is designed to operate from a
single 3 V to 5 V or a dual ±5 V supply. Built with Analog’s robust
CBCMOS process, this monolithic DAC offers the user low
cost, and ease-of-use in single or dual-supply systems.
The applied external reference VREF determines the full-scale
output voltage. Valid VREF values include VSS < VREF < VDD that
result in a wide selection of full-scale outputs. For multiplying
applications ac inputs can be as large as ± 5 VP.
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller-compatible inputs using serial-
data-in (SDI), clock (CLK), and a chip-select (CS). A common
level-sensitive load-DAC strobe (LDAC) input allows simulta-
neous update of all DAC outputs from previously loaded Input
Registers. Additionally, an internal power ON reset forces the
output voltage to zero at system turn ON. An external asynchro-
nous reset (RS) also forces all registers to the zero code state. A
programmable power-shutdown feature reduces power dissipa-
tion on unused DACs.
Both parts are offered in the same pinout to enable users to
select the appropriate resolution for their application without
redesigning the layout. For 8-bit resolution applications see the
pin compatible AD7304 product.
The AD7398/AD7399 is specified over the extended industrial
(–40°C to +125°C) temperature range. Parts are available in
wide body SOIC-16 and ultracompact thin 1.1 mm TSSOP-
16 packages.
Quad, Serial-Input
12-Bit/10-Bit DACs
AD7398/AD7399
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFB VREFA
SERIAL
REGISTER
CS
SDI
CLK
INPUT
REG A
DAC A
REGISTER
DAC A
INPUT
REG B
DAC B
REGISTER
DAC B
INPUT
REG C
DAC C
REGISTER
DAC C
VOUTA
VOUTB
VOUTC
12/10
POWER
ON RESET
INPUT
REG D
DAC D
REGISTER
DAC D
VOUTD
VSS RS
LDAC VREFC VREFD GND
0.50
0.40
0.30
0.20
VDD = +5V
VSS = –5V
VREF = +2.5V
TA = 25؇C
0.10
0
–0.10
–0.20
–0.30
–0.40
–0.50
0
512 1024 1536 2048 2560 3072 3584 4096
CODE – Decimal
Figure 1. AD7398 DNL vs. Code (TA = 25°C)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD7398/AD7399
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Thermal Resistance θJA
16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . 158°C/W
16-Lead Thin Shrink Surface Mount (RU-16) . . . 180°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . (TJ Max–TA)/θJA
Operating Temperature Range . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
R-16 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C
RU-16 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . 224°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Resolution
(Bits)
Temperature
Range
Package
Description
AD7398BR
AD7398BR-REEL7
AD7398BRU-REEL7
AD7399BR
AD7399BR-REEL7
AD7399BRU-REEL7
12
12
12
10
10
10
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
SOL-16
SOL-16
TSSOP-16
SOL-16
SOL-16
TSSOP-16
The AD7398 contains 3254 transistors. The die size measures 108 mil × 144 millimeters.
Package
Option
R-16
R-16
RU-16
R-16
R-16
RU-16
Container
Quantity
48
1,000
1,000
48
1,000
1,000
SDI
CLK
CS
LDAC
CLK
LDAC
CS
SA SD A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
tCSS
tDS tDH
tCH tCL
tCSH
IN
REG
LD
tLDH
tLDS
Figure 2. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)
tLDAC
tLDS
tCSS
tCH tCL
tCSH
tLDH
1/fCLK
tLDAC
tCSS
tLDS
Figure 3. Continuous Clock Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7398/AD7399 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. 0
4페이지 TERMINOLOGY
Relative Accuracy, INL
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in TPC 1.
Differential Nonlinearity, DNL
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maxi-
mum ensures monotonicity. TPC 3 illustrates a typical DNL
versus code plot.
Zero-Scale Error, VZSE
Zero-scale error is a measure of the output voltage error from
zero voltage when zero code is loaded to the DAC register.
Full-Scale Error, VFSE
Full-scale error is a measure of the output voltage error from full-
scale voltage when full-scale code is loaded to the DAC register.
Full-Scale Temperature Coefficient, TCVFS
This is a measure of the change in full-scale error with a change
in temperature. It is expressed in ppm/°C or mV/°C.
DAC Glitch Impulse, Q
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
AD7398/AD7399
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition (midscale transition). A plot of the
glitch impulse is shown in TPC 10.
Digital Feedthrough, QDF
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. CS is held
high, while the CLK and SDI signals are toggled. It is speci-
fied in nV-s and is measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa. A typi-
cal plot of digital feedthrough is shown in TPC 11.
Power Supply Sensitivity, PSS
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
sensitivity is quoted in terms of % change in output per %
change in VDD for full-scale output of the DAC. VDD is varied
by ± 10%.
Reference Feedthrough, VOUT/VREF
This is a measure of the feedthrough from the VREF input to
the DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in dB or mV p-p.
REV. 0
–7–
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |