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PDF AD74322 Data sheet ( Hoja de datos )
| Número de pieza | AD74322 | |
| Descripción | Low Cost/ Low Power Stereo Audio Analog Front End | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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LowCost,LowPower
StereoAudioAnalogFrontEnd
Preliminary Technical Data
AD74322
FEATURES
2.5V Stereo Audio Codec with 3.3 V Tolerant Digital
Interface
FUNCTIONALBLOCKDIAGRAM
DVDD1(EXT) DVDD2(INT) CLKIN
AVDD
Supports 96 kHz Sample Rates
Supports 16/18 /20/24-Bit Word Lengths
Multibit Sigma Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs - Least Sensitive to Jitter
CDIN
CDOUT
CCLK
CLATCH
SPI
Port
Control
Block
ADC
CHANNEL 1
ADC
CHANNEL 2
Performance (20 Hz to 20 kHz)
ASDATA/SDO
90 dB ADC and DAC SNR
DSDATA/SDI
YDigitally Programmable Input/Output Gain
LRCLK/SDIFS
On-chip Volume Controls Per Output Channel
RHardware and Software Controllable Clickless Mute
ASupports 256xFs, 512xFs and 768xFs Master Mode Clocks
INMaster Clock Pre-Scaler for use with DSP master clocks
SDOFS
BCLK/SCLK
LFlexible Serial Data Port with Right-Justified, Left-
IM AJustified, I2S-Compatible and DSP Serial Port Modes
Supports Packed Data Mode (“TDM”) for cascading
L ICdevices.
E NOn-Chip Reference
CDIN
R16, 20 and 24-Lead SOIC, SSOP and TSSOP Package
CDOUT
P Hoptions.
CCLK
EC TAAPPLICATIONS
T ADigital Video Camcorders (DVC)
DPortable Audio Devices (Walkman etc)
CLATCH
ASDATA
I2S
Port
Reference
DGND
REFCAP
DVDD1(EXT) DVDD2(INT) CLKIN
SPI
Port
Control
Block
Audio Processing
Voice Processing
Conference Phones
General Purpose Analog I/O
DSDATA
LRCLK
BCLK
I2S
Port
Reference
DAC
CHANNEL 1
DAC
CHANNEL 2
AGND
AVDD
ADC
CHANNEL 1
ADC
CHANNEL 2
DAC
CHANNEL 1
DAC
CHANNEL 2
VIN1P
VIN1N
VIN2P
VIN2N
VOUT1P
VOUT1N
VOUT2P
VOUT2N
VIN1
VIN2
VOUT1
VOUT2
GENERAL DESCRIPTION
The AD74322 is a front-end processor for general purpose
audio and voice applications. It features two multi-bit Σ∆
A/D conversion channels and two multi-bit Σ∆ D/A
conversion channels. Each ADC channel provides >85 dB
signal-to-noise ratio while each DAC channel provides
>90 dB, both over an audio signal bandwidth.
The AD74322 is particularly suitable for a variety of ap-
plications where stereo input and output channels are
required, including audio sections of Digital Video
Camcorder, portable personal audio devices and the
analog front ends of conference phones . Its high quality
performance also make it suitable for speech and telephony
applications such as speech recognition and synthesis and
modern feature phones.
SDO
SDI
SDIFS
SDOFS
SCLK
DGND
REFCAP
DVDD1(EXT) DVDD2(INT) CLKIN
Control
Block
Data
Port
Reference
AGND
AVDD
ADC
CHANNEL 1
ADC
CHANNEL 2
DAC
CHANNEL 1
DAC
CHANNEL 2
VIN1
VIN2
VOUT1
VOUT2
DGND
REFCAP
AGND
REV. Pr D 03/00
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
1 page  
PRELIMINARY TECHNICAL DATA
ORDERING GUIDE
Model
AD74322DAR
AD74322DARU
AD74322AAR
AD74322AARU
AD74322AAR
AD74322AARU
Range
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
Package
R-16
RU-16
R-20
RU-20
R-24
RU-24
AD74322
IMINARYLCAUTION
AESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
L ICaccumulate on the human body and test equipment and can discharge without detection.
EAlthough the XX0000 features proprietary ESD protection circuitry, permanent damage may
R Noccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
P Hprecautions are recommended to avoid performance degradation or loss of functionality.
TEC DATAVINN1 1
24 VOUTN1
VINN2 2
23 VOUTN2
VINN1 3
22 VOUTN1
VINP1 4
21 VOUTP1
REFCAP 5
20 AVDD
AGND 6
19 RESET
DGND 7
18 SDO
DVDD2 8
17 SDFS
DVDD1
9
TOP VIEW
(Not to Scale)
16 SDI
MCLK 10
15 SCLK
CCLK 11
14 COUT
CIN 12
13 CLATCH
VINP2 1
VINP1 2
20 VOUTP2
19 VOUTP1
REFCAP 3
18 AVDD
AGND 4
17 RESET
DGND 5
16 SDO
DVDD2 6
DVDD1
7
TOP VIEW
(Not to Scale)
MCLK 8
15 SDFS
14 SDI
13 SCLK
CCLK 9
12 COUT
CIN 10
11 CLATCH
VINP2 1
VINP1 2
REFCAP 3
AGND 4
16 VOUTP2
15 VOUTP1
14 AVDD
13 RESET
DGND 5
12 SDO
DVDD2 6
DVDD1
7
TOP VIEW
(Not to Scale)
MCLK 8
11 SDFS
10 SDI
9 SCLK
Pr D 03/00
–5–
5 Page 
PRELIMINARY TECHNICAL DATA
AD74322
INTERFACING
Data in and out of the Control Port go through a 16-bit
TheAD74322featurestwoseparateinterfaces,ControlandData,which shift register whose contents are mapped to the internal
areusedtoprogramcontrolsettingsandsend/receivesampledata
registers using the mapping scheme of Figure
respectively.TheControlinterfaceisimplementedusinganSPItype
<ContPortMap>. A 16-bit word received by the Control
protocolbuttransfers16-bitsperframe.TheDatainterfaceuseseithera Port is decoded as a read or write to a register address set
DSPor I2Sprotocoltotransferstereodatasamplesbetweencontroller by bits 15 - 12. This 4-bit register address selects 1 of 16
andcodec.TheDSPcompatibleinterfacemodeallowsdatasamplestobe registers as shown in Table <ContRegMap>. Bit 11
transferredinaprotocolthatissupportedbytheserialinterfacesofmost selects whether a register read or write is requested -
fixed-andfloating-pointDSPs.
Write = 0, Read = 1. Bit-10 is reserved. Bits 9 through 0
InordertoreduceperipheralrequirementswheninterfacingtheAD74322
with the host DSP, the DSP mode allows the DSP to send both data and
contain register data. Each Control register’s contents are
detailed below.
controlinformationtothedeviceviathedatainterface.Thisisthedefault DataInterface
modeandrequiresuserstoonlyuseasingleDSPSPORTtobothcontrol Therearetwomodesofoperationofthedatainterface:DSPmodeand
the device and service it with data samples.
I2S mode. The default mode of the data interface is a DSP mode which
ControlInterface
combines control and data functions in a single protocol. This is to reduce
Control of the AD74322 operation is via a set of 16 Control Registers
whichareprogrammedthroughtheControlPort.TheControlPort
Yprotocol is similar to the SPIÒ protocol with the exception that 16-bits of
Rdata are transferred per frame. The Control Port consists of the following
pins: CCLK - Control Port Serial Clock, CLATCH - Control Port Latch
Aor Frame signal, CDIN - Control Port Serial Data In and CDOUT -
INControlPortDataOut.CLATCHisaframingsignalthatisactivelow.
LWhen asserted, it gates the other interface lines as being active. CCLK is
IM AusedtoclockinputdataonCDINandclockoutput(readback)dataon
L ICCDOUT.Figure<Control_Interface>detailstheconnectivityofthe
ControlPorttoacontrollerandFigure<Control_Timing>detailsthe
E Ninterfacetiming.
PRTECHDATAAD743xx
theperipheraloverheadrequiredontheDSPwheninterfacingtothe
AD74322. This mode operates in a standard DSP serial format. In I2S
mode the data interface streams audio data samples being sent to or
receivedfromtheDACsandADCsrespectively,usingtheI2Sserial
protocol.
In either mode it can be configured as either a master or slave device
ensuringconnectivitytothelargestnumberofhostprocessors.
DSPMode
TheDSPmodeallowsinterfacingtomostfixed-andfloating-pointDSPs
as well as other processors such as RISCs etc that having serial ports that
supportsynchronouscommunications.Thekeyfeatureofsynchronous
DSP communications is that the serial data is framed by a separate Frame
Syncsignal.Figures<Data_DSP_Slave>and<Data_DSP_Master>detail
connectivity in Master Mode (codec is master) and Slave Mode (codec is
slave)respectively.
CDIN CLATCH CCLK CDOUT
AD743xx
(MASTER)
TFS
LRCLK/SDIFS
CONTROLLER
DSP
(SLAVE)
DT
SCLK
DR
RFS
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
SDOFS
Figure <Control_Interface>
Figure <Data_DSP_Slave>
CCLK
CDIN
MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
CDOUT
MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
CLATCH
Pr D 03/00
Figure <Control_Timing>
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD74322.PDF ] | |
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