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PDF AD745 Data sheet ( Hoja de datos )
| Número de pieza | AD745 | |
| Descripción | Ultralow Noise/ High Speed/ BiFET Op Amp | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Ultralow Noise,
High Speed, BiFET Op Amp
FEATURES
ULTRALOW NOISE PERFORMANCE
2.9 nV/͙Hz at 10 kHz
0.38 V p-p, 0.1 Hz to 10 Hz
6.9 fA/͙Hz Current Noise at 1 kHz
EXCELLENT AC PERFORMANCE
12.5 V/s Slew Rate
20 MHz Gain Bandwidth Product
THD = 0.0002% @ 1 kHz
Internally Compensated for Gains of +5 (or –4) or
Greater
EXCELLENT DC PERFORMANCE
0.5 mV max Offset Voltage
250 pA max Input Bias Current
2000 V/mV min Open Loop Gain
Available in Tape and Reel in Accordance with
EIA-481A Standard
APPLICATIONS
Sonar
Photodiode and IR Detector Amplifiers
Accelerometers
Low Noise Preamplifiers
High Performance Audio
PRODUCT DESCRIPTION
The AD745 is an ultralow noise, high speed, FET input
operational amplifier. It offers both the ultralow voltage noise
and high speed generally associated with bipolar input op amps
and the very low input currents of FET input devices. Its 20
MHz bandwidth and 12.5 V/µs slew rate makes the AD745 an
ideal amplifier for high speed applications demanding low noise
and high dc precision. Furthermore, the AD745 does not
exhibit an output phase reversal.
1000
100
RSOURCE
RSOURCE
EO
OP37 &
RESISTOR
(—)
AD745 & RESISTOR
OR
OP37 & RESISTOR
10
AD745 + RESISTOR
()
RESISTOR NOISE ONLY
(– – –)
1
100
REV. C
1k
10k
100k
1M
SOURCE RESISTANCE – Ω
10M
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AD745
CONNECTION DIAGRAMS
8-Pin Plastic Mini-DIP (N) & 16-Pin SOIC (R) Package
8-Pin Cerdip (Q) Packages
OFFSET
NULL 1
– IN 2
+IN 3
AD745
TOP VIEW
–VS 4
NC 1
8 NC
7 +VS
OFFSET 2
NULL
– IN 3
6 OUTPUT
5 OFFSET
NULL
NC 4
+IN 5
–VS 6
16 NC
AD745 15 NC
14 NC
13 +VS
12 OUTPUT
11
OFFSET
NULL
NC = NO CONNECT
NC 7 TOP VIEW 10 NC
NC 8
9 NC
The AD745’s guaranteed, tested maximum input voltage noise
of 4 nV/√Hz at 10 kHz is unsurpassed for a FET-input mono-
lithic op amp, as is its maximum 1.0 µV p-p noise in a 0.1 Hz to
10 Hz bandwidth. The AD745 also has excellent dc perfor-
mance with 250 pA maximum input bias current and 0.5 mV
maximum offset voltage.
The internal compensation of the AD745 is optimized for
higher gains, providing a much higher bandwidth and a faster
slew rate. This makes the AD745 especially useful as a
preamplifier where low level signals require an amplifier that
provides both high amplification and wide bandwidth at these
higher gains. The AD745 is available in five performance
grades. The AD745J and AD745K are rated over the
commercial temperature range of 0°C to +70°C. The AD745A
and AD745B are rated over the industrial temperature range of
–40°C to +85°C. The AD745S is rated over the military
temperature range of –55°C to +125°C and is available
processed to MIL-STD-883B, Rev. C.
The AD745 is available in 8-pin plastic mini-DIP, 8-pin cerdip,
16-pin SOIC, or in chip form.
120
120
100
80
PHASE
100
80
60
GAIN
40
60
40
20 20
00
–20
100
1k
10k 100k 1M
FREQUENCY – Hz
–20
10M 100M
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
120 120
100 100
PHASE
80 80
60
GAIN
40
60
40
20 20
00
–20 –20
100 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
Figure 10. Open-Loop Gain and
Phase vs. Frequency
120
110
100
90
80
Vcm = ±10V
70
60
50
100
1k 10k 100k 1M
FREQUENCY – Hz
10M
Figure 13. Common-Mode Rejection
vs. Frequency
Typical Characteristics–AD745
14
12
CLOSED-LOOP GAIN = +5
10
150
RL = 2kΩ
140
130
120
100
8
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – °C
Figure 11. Slew Rate vs.
Temperature
80
0
5 10 15
SUPPLY VOLTAGE ± VOLTS
20
Figure 12. Open-Loop Gain vs.
Supply Voltage
120
100
+ SUPPLY
80
60 – SUPPLY
40
20
0
100 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
Figure 14. Power Supply Rejection
vs. Frequency
35
30
25
R L = 2kΩ
20
15
10
5
0
10k
100k
1M
FREQUENCY – Hz
10M
Figure 15. Large Signal Frequency
Response
–40 1.0 100
–60 0.1
–80
–100
GAIN = +10
GAIN = +100
–120
GAIN = –4
–140
10
100 1k
10k
FREQUENCY – Hz
0.01
0.001
0.0001
0.00001
100k
Figure 16. Total Harmonic Distortion
vs. Frequency
CLOSED-LOOP GAIN = +5
10
1.0
0.1
10
100 1k 10k 100k 1M
FREQUENCY – Hz
10M
Figure 17. Input Noise Voltage
Spectral Density
1k
100
10
1.0
1
10 100 1k 10k
FREQUENCY – Hz
100k
Figure 18. Input Noise Current
Spectral Density
REV. C
–5–
5 Page 
Design Considerations for I-to-V Converters
There are some simple rules of thumb when designing an I-V
converter where there is significant source capacitance (as with a
photodiode) and bandwidth needs to be optimized. Consider the
circuit of Figure 37. The high frequency noise gain (1 + CS/CL)
is usually greater than five, so the AD745, with its higher slew
rate and bandwidth is ideally suited to this application.
Here both the low current and low voltage noise of the AD745
can be taken advantage of, since it is desirable in some instances
to have a large RF (which increases sensitivity to input current
noise) and, at the same time, operate the amplifier at high noise
gain.
RF
INPUT SOURCE: PHOTO DIODE,
ACCELEROMETER, ECT.
CL
AD745
1µF +
0.01
µF
–12V
1
2
0.01
µF
+12V
DIGITAL
INPUTS
3
4
5
6
7
–12V
8
0.01µF
+12V
AD1862
20 BIT D/A
CONVERTER
16
0.01µF
15
+12V
14 10µF
13 +
ANALOG
COMMON
0.1µF
OUTPUT
3kΩ
TOP VIEW
12
11
10
9
AD745
0.1µF
–12V
3 POLE
LOW
PASS
FILTER
DIGITAL
COMMON
100pF
2000pF
I S R B C S AD745
Figure 37. A Model for an l-to-V Converter
In this circuit, the RF CS time constant limits the practical
bandwidth over which flat response can be obtained, in fact:
fB ≈
fC
2π RFCS
where:
fB = signal bandwidth
fC = gain bandwidth product of the amplifier
With CL ≈ 1/(2 π RF CS) the net response can be adjusted to a
provide a two pole system with optimal flatness that has a corner
frequency of fB. Capacitor CL adjusts the damping of the
circuit’s response. Note that bandwidth and sensitivity are
directly traded off against each other via the selection of RF. For
example, a photodiode with CS = 300 pF and RF = 100 kΩ will
have a maximum bandwidth of 360 kHz when capacitor
CL ≈ 4.5 pF. Conversely, if only a 100 kHz bandwidth were
required, then the maximum value of RF would be 360 kΩ and
that of capacitor CL still ≈ 4.5 pF.
In either case, the AD745 provides impedance transformation,
the effective transresistance, i.e., the I/V conversion gain, may be
augmented with further gain. A wideband low noise amplifier
such as the AD829 is recommended in this application.
This principle can also be used to apply the AD745 in a high
performance audio application. Figure 38 shows that an I-V
converter of a high performance DAC, here the AD1862, can be
designed to take advantage of the low voltage noise of the
AD745 (2.9 nV/͙Hz) as well as the high slew rate and
bandwidth provided by decompensation. This circuit, with
component values shown, has a 12 dB/octave rolloff at 728 kHz,
with a passband ripple of less than 0.001 dB and a phase
deviation of less than 2 degrees @ 20 kHz.
Figure 38. A High Performance Audio DAC Circuit
An important feature of this circuit is that high frequency
energy, such as clock feedthrough, is shunted to common via a
high quality capacitor and not the output stage of the amplifier,
greatly reducing the error signal at the input of the amplifier and
subsequent opportunities for intermodulation distortions.
40
30
UNBALANCED
20
10 BALANCED
2.9nV/√ Hz
0
10
100
INPUT CAPACITANCE – pF
1000
Figure 39. RTI Noise Voltage vs. Input Capacitance
BALANCING SOURCE IMPEDANCES
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD745. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 39, noise
performance will be optimized. Figure 40 shows the required
external components for noninverting (A) and inverting (B)
configurations.
REV. C
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD745.PDF ] | |
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