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AD7467 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7467은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 AD7467 기능
기능 1.8 V/ Micro-Power/ 8/10/12-Bit ADCs in 6 Lead SOT-23
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AD7467 데이터시트, 핀배열, 회로
a
pecifications
1.8 V, Micro-Power,
8/10/12-Bit ADCs in 6 Lead SOT-23
Preliminary Technical Data
AD7466/AD7467/AD7468
FEATURES
Specified for VDD of 1.8 V to 3.6 V
Low Power:
0.9 mW max at 60 kSPS with 3.6 V Supplies
0.4 mW max at 100 kSPS with 1.8 V Supplies
Fast Throughput Rate: 100 kSPS
Wide Input Bandwidth:
70dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI/QSPI/µWire/DSP Compatible
Standby Mode: 0.5 µA max
6-Lead SOT-23 Package and 8 lead µSOIC
APPLICATIONS
Battery Powered Systems
Medical Instruments
Ramote Data Acquisition
Isolated Data Acquisition
GENERAL DESCRIPTION
The AD7466/AD7467/AD7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs re-
spectively. The parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. The parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. There are no pipelined delays
associated with the part.
The AD7466/AD7467/AD7468 use advanced design tech-
niques to achieve very low power dissipation at high
throughput rates.
The reference for the part is taken internally from VDD.
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to VDD. The
conversion rate is determined by the SCLK.
FUNCTIONAL BLOCK DIAGRAM
VDD
12/10/8-BIT
VIN T/H SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7466/67/68
GND
SCLK
SDATA
CS
PRODUCT HIGHLIGHTS
1. Specified for Supply voltages of 1.8 V to 3.6 V
2. 8/10/12-Bit ADCs in a SOT-23 package.
3. High Throughput with Low Power Consumption
4. Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5 µA max when in powerdown.
5. Reference derived from the power supply.
6. No Pipeline Delay
The part features a standard successive-approximation
ADC with accurate control of the conversions via a CS
input.
REV. PrC 07/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001




AD7467 pdf, 반도체, 판매, 대치품
pecifications
AD7468–SPECIFICATIONS1
Parameter
(VDD = 1.8 V to 3.6 V, fSCLK = 2.4 MHz, fSAMPLE = 100 kSPS unless otherwise noted; TA =
TMIN to TMAX, unless otherwise noted.)
B Version1, 2 Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY2
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Total Unadjusted Error (TUE)
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN2,3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3, 4
Output Coding
49
–65
–65
–68
–68
10
30
TBD
TBD
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
fIN =30 kHz Sine Wave, fSAMPLE=100kSPS
fa = 29.1 kHz, fb = 29.9 kHz
@ 3 dB
@ 0.1 dB
8
±0.5
±0.5
±0.5
±0.5
±0.5
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed No Missed Codes to 8 Bits
0 to VDD
±1
30
V
µA max
pF typ
0.7(VDD)
0.4
±1
±1
10
V min
V max
µA max
µA typ
pF max
VDD = 1.8 to 3.6 V
Typically 10 nA, VIN = 0 V or VDD
VDD – 0.2
0.2
V min
V max
±10 µA max
10 pF max
Straight (Natural) Binary
ISOURCE = 200 µA; VDD = 1.8 V to 3.6 V
ISINK = 200 µA
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
IDD
Normal Mode (Static)
Power-Down Mode
Power Dissipation5
Normal Mode (Operational)
Power-Down
NOTES
1Temperaturerangesasfollows:BVersions:–40°Cto+85°C.
2SeeTerminology.
3Sampletestedat25°Ctoensurecompliance.
4SeePowerVersusThroughputRatesection.
Specificationssubjecttochangewithoutnotice.
4.166
TBD
100
1.8/3.6
350
200
0.5
80
TBD
TBD
1.5
0.9
µs max
ns max
kSPS max
10 SCLK Cycles with SCLK at 2.4 MHz
See Serial Interface Section
V min/max
µA max
µA max
µA max
µA max
Digital I/Ps = 0 V or VDD
VDD = 3V. SCLK On or Off
VDD = 1.8 V . SCLK On or Off
SCLK Off
SCLK On
mW max
mW max
µW max
µW max
VDD = 3 V. fSAMPLE = TBD
VDD = 1.8 V. fSAMPLE = TBD
VDD = 3 V. SCLK Off
VDD = 1.8 V. SCLK Off
–4– REV. PrC

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AD7467 전자부품, 판매, 대치품
pecifications
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
For the AD7466/67/68 the endpoints of the transfer
function are zero scale, a point 1 LSB below the first
code transition, and full scale, a point 1 LSB above the
last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . .
000) to (00 . . . 001) from the ideal, i.e AGND + 1
LSB.
Gain Error
This is the deviation of the last code transition (111 . . .
110) to (111 . . . 111) from the ideal (i.e., VREF – 1LSB)
after the offset error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode at the
end of conversion. Track/Hold acquisition time is the
time required for the output of the track/hold amplifier
to reach its final value, within ±0.5 LSB, after the end
of conversion. See serial interface timing section for
more details.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distor-
tion) at the output of the A/D converter. The signal is
the rms amplitude of the fundamental. Noise is the sum
of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc. The ratio is dependent on
the number of quantization levels in the digitization
process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is
given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-
bit converter this is 62dB.
AD7466/AD7467/AD7468
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7466/
AD7467/AD7468, it is defined as:
THD (dB ) = 20 log
V
2
2
+
V
2
3
+
V
2
4
+ V52
+V
2
6
V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7466/AD7467/AD7468 are tested using the CCIF
standard where two input frequencies are used. In this
case, the second order terms are usually distanced in fre-
quency from the original sine waves while the third order
terms are usually at a frequency close to the input frequen-
cies. As a result, the second and third order terms are
specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
REV. PrC
–7–

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