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AD7475 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7475은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 AD7475 기능
기능 1 MSPS / 12-Bit ADCs
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AD7475 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power
4.5 mW max at 1 MSPS with 3 V supplies
10.5 mW max at 1 MSPS with 5 V supplies
Wide input bandwidth: 68 dB SNR at 300 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI-/QSPI™-/MICROWIRE-/DSP-compatible
On-board reference: 2.5 V (AD7495 only)
Standby mode: 1 μA max
8-lead MSOP and SOIC packages
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
GENERAL DESCRIPTION
The AD7475/AD74951 are 12-bit, high speed, low power,
successive-approximation ADCs that operate from a single
2.7 V to 5.25 V power supply with throughput rates up to 1 MSPS.
They contain a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies above 1 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and conversion is initiated at this point.
The conversion time is determined by the SCLK frequency.
There are no pipeline delays associated with the device.
The AD7475/AD7495 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
With 3 V supplies and a 1 MSPS throughput rate, the AD7475
consumes just 1.5 mA, while the AD7495 consumes 2 mA. With
5 V supplies and 1 MSPS, the current consumption is 2.1 mA
for the AD7475 and 2.6 mA for the AD7495.
The analog input range for the devices is 0 V to REF IN. The
2.5 V reference for the AD7475 is applied externally to the REF IN
pin, while the AD7495 has an on-board 2.5 V reference.
1Protected by U.S. Patent No. 6,681,332
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
1 MSPS,12-Bit ADCs
AD7475/AD7495
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN
REF IN
T/H 12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AD7475
VDD
CONTROL
LOGIC
GND
SCLK
SDATA
CS
VDRIVE
VIN
REF OUT
T/H
BUF
2.5V
REFERENCE
AD7495
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
SCLK
SDATA
CS
VDRIVE
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD7475 offers 1 MSPS throughput rates with 4.5 mW
power consumption.
2. Single-supply operation with VDRIVE function. The
AD7475/AD7495 operate from a single 2.7 V to 5.25 V
supply. The VDRIVE function allows the serial interface to
connect directly to either 3 V or 5 V processor systems
independent of VDD.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The devices also feature shutdown modes
to maximize power efficiency at lower throughput rates.
This allows the average power consumption to reduce while
not converting. Power consumption is 1 μA when in full
shutdown.
4. No pipeline delay. The devices feature a standard successive
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2001-2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD7475 pdf, 반도체, 판매, 대치품
AD7475/AD7495
Parameter
POWER REQUIREMENTS
VDD
VDRIVE
IDD3
Normal Mode (Static)
Normal Mode (Operational)
Partial Power-Down Mode
Partial Power-Down Mode
Full Power-Down Mode
Power Dissipation3
Normal Mode (Operational)
Partial Power-Down (Static)
Full Power-Down
A Version1
2.7/5.25
2.7/5.25
750
2.1
1.5
450
100
1
10.5
4.5
500
300
5
3
1 Temperature ranges for A, B versions: −40°C to +85°C.
2 Guaranteed by initial characterization.
3 See the Power vs. Throughput Rate section.
B Version1
2.7/5.25
2.7/5.25
750
2.1
1.5
450
100
1
10.5
4.5
500
300
5
3
Unit
V min/max
V min/max
µA typ
mA max
mA max
µA typ
µA max
µA max
mW max
mW max
µW max
µW max
µW max
µW max
Data Sheet
Test Conditions/Comments
Digital inputs = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS
VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS
fSAMPLE = 100 kSPS
Static
SCLK on or off
VDD = 5 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Rev. C | Page 4 of 24

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AD7475 전자부품, 판매, 대치품
Data Sheet
AD7475/AD7495
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
fSCLK2
tCONVERT
tQUIET
t2
t3 3
t43
t5
t6
t7
t8 4
t94
tPOWER-UP
Limit at TMIN, TMAX
10
20
16 × tSCLK
800
100
10
22
40
0.4 tSCLK
0.4 tSCLK
10
10
45
20
20
650
Unit
kHz min
MHz max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
µs max
µs max
Description
tSCLK = 1/fSCLK
fSCLK = 20 MHz
Minimum quiet time required between conversions
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
SCLK falling edge to SDATA high impedance
CS rising edge to SDATA high impedance
Power-up time from full power-down (AD7475)
Power-up time from full power-down (AD7495)
1 Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are
the true bus relinquish times of the device and are independent of the bus loading.
Rev. C | Page 7 of 24

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