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PDF AD7475 Data sheet ( Hoja de datos )
| Número de pieza | AD7475 | |
| Descripción | 1 MSPS / 12-Bit ADCs | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power
4.5 mW max at 1 MSPS with 3 V supplies
10.5 mW max at 1 MSPS with 5 V supplies
Wide input bandwidth: 68 dB SNR at 300 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI-/QSPI™-/MICROWIRE-/DSP-compatible
On-board reference: 2.5 V (AD7495 only)
Standby mode: 1 μA max
8-lead MSOP and SOIC packages
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
GENERAL DESCRIPTION
The AD7475/AD74951 are 12-bit, high speed, low power,
successive-approximation ADCs that operate from a single
2.7 V to 5.25 V power supply with throughput rates up to 1 MSPS.
They contain a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies above 1 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and conversion is initiated at this point.
The conversion time is determined by the SCLK frequency.
There are no pipeline delays associated with the device.
The AD7475/AD7495 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
With 3 V supplies and a 1 MSPS throughput rate, the AD7475
consumes just 1.5 mA, while the AD7495 consumes 2 mA. With
5 V supplies and 1 MSPS, the current consumption is 2.1 mA
for the AD7475 and 2.6 mA for the AD7495.
The analog input range for the devices is 0 V to REF IN. The
2.5 V reference for the AD7475 is applied externally to the REF IN
pin, while the AD7495 has an on-board 2.5 V reference.
1Protected by U.S. Patent No. 6,681,332
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
1 MSPS,12-Bit ADCs
AD7475/AD7495
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN
REF IN
T/H 12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AD7475
VDD
CONTROL
LOGIC
GND
SCLK
SDATA
CS
VDRIVE
VIN
REF OUT
T/H
BUF
2.5V
REFERENCE
AD7495
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
SCLK
SDATA
CS
VDRIVE
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD7475 offers 1 MSPS throughput rates with 4.5 mW
power consumption.
2. Single-supply operation with VDRIVE function. The
AD7475/AD7495 operate from a single 2.7 V to 5.25 V
supply. The VDRIVE function allows the serial interface to
connect directly to either 3 V or 5 V processor systems
independent of VDD.
3. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The devices also feature shutdown modes
to maximize power efficiency at lower throughput rates.
This allows the average power consumption to reduce while
not converting. Power consumption is 1 μA when in full
shutdown.
4. No pipeline delay. The devices feature a standard successive
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2001-2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD7475/AD7495
AD7495 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
(SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
A Version1
68
−75
−76
−78
−78
10
50
8.3
1.3
12
±1.5
±0.5
+1.5/−0.9
B Version1
68
−75
−76
−78
−78
10
50
8.3
1.3
12
±1
±0.5
+1.5/−0.9
Unit
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB typ
LSB max
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage
REF OUT Impedance
REF OUT Temperature Coefficient
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN2
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance2
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
±0.6 ±0.6 LSB typ
±8 ±8 LSB max
±7 ±7 LSB max
0 to 2.5
±1
20
0 to 2.5
±1
20
V
µA max
pF typ
2.4625/2.5375
10
50
2.4625/2.5375
10
50
V min/max
Ω typ
ppm/°C typ
VDRIVE − 1
0.4
±1
10
VDRIVE − 1
0.4
±1
10
V min
V max
µA max
pF max
VDRIVE − 0.2
0.4 0.4
±10 ±10
10 10
Straight (Natural) Binary
V min
V max
µA max
pF max
800 800 ns max
300 300 ns max
325 325 ns max
1 1 MSPS max
Test Conditions/Comments
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS
@ 3 dB
@ 0.1 dB
@ 5 V (typ @ 3 V)
@ 25°C
@ 5 V guaranteed no missed codes to
12 bits (typ @ 3 V)
@ 25°C
Typically ±2.5 LSB
Typically ±2.5 LSB
Typically 10 nA, VIN = 0 V or VDRIVE
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V
ISINK = 200 µA
16 SCLK cycles with SCLK @ 20 MHz
Sine wave input
Full-scale step input
See the Serial Interface section
Rev. C | Page 5 of 24
5 Page 
Data Sheet
TERMINOLOGY
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, a point ½ LSB below the
first code transition, and full scale, a point ½ LSB above the last
code transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
This is the deviation of the last code transition (111. . . 110) to
(111. . . 111) from the ideal (that is, VREF − 1.5 LSB) after the
offset error has been adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode on the
13th SCLK rising edge (see the Serial Interface section). The
track-and-hold acquisition time is the minimum time required
for the track-and-hold amplifier to remain in track mode for its
output to reach and settle to within 0.5 LSB of the applied input
signal, given a step change to the input signal.
Signal-to-Noise and Distortion Ratio (SINAD)
The measured ratio of signal-to-noise and distortion at the
output of the analog-to-digital converter (ADC). The signal is
the rms amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent on the number of
quantization levels in the digitization process; the more levels,
the smaller the quantization noise. The theoretical SINAD ratio
for an ideal N-bit converter with a sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76)dB
For a 12-bit converter, the SINAD is 74 dB.
AD7475/AD7495
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7475/AD7495, THD is defined as
THD (dB) = 20 log
V22 + V32 + V42 + V52 +V62
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products at
sum and difference frequencies of mfa ± nfb where m, n = 0, 1,
2, 3, etc. Intermodulation distortion terms are those for which
neither m nor n is equal to zero. For example, the second-order
terms include (fa + fb) and (fa − fb), while the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
The AD7475/AD7495 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. Like THD, intermodulation distortion is calculated
as the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals, expressed in dBs.
Rev. C | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD7475.PDF ] | |
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