PDF AD421 Data sheet ( Hoja de datos )

Número de pieza	AD421
Descripción	Loop-Powered 4 mA to 20 mA DAC
Fabricantes	Analog Devices
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No Preview Available ! a Loop-Powered 4 mA to 20 mA DAC AD421 FEATURES 4 mA to 20 mA Current Output HART® Compatible 16-Bit Resolution and Monotonicity ؎0.01% Integral Nonlinearity 5 V or 3 V Regulator Output 2.5 V and 1.25 V Precision Reference 750 ␮A Quiescent Current max Programmable Alarm Current Capability Flexible High Speed Serial Interface 16-Lead SOIC and PDIP Packages GENERAL DESCRIPTION The AD421 is a complete, loop-powered, digital to 4 mA to 20 mA converter, designed to meet the needs of smart trans- mitter manufacturers in the Industrial Control industry. It pro- vides a high precision, fully integrated, low cost solution in a compact 16-lead package. The AD421 is ideal for extending the resolution of smart 4 mA to 20 mA transmitters at very low cost. The AD421 includes a selectable regulator that is used to power itself and other devices in the transmitter. This regulator pro- vides either a +5 V, +3.3 V or +3 V regulated output voltage. The part also contains +1.25 V and +2.5 V precision references. The AD421 thus eliminates the need for a discrete regulator and voltage reference. The only external components required are a number of passive components and a pass transistor to span large loop voltages. The AD421 can be used with standard HART FSK protocol communication circuitry without any degradation in specified performance. The high speed serial interface is capable of oper- ating at 10 Mbps and allows for simple connection to com- monly-used microprocessors and microcontrollers via a standard three-wire serial interface. The sigma-delta architecture of the DAC guarantees 16-bit monotonicity while the integral nonlinearity for the AD421 is ± 0.01%. The part provides a zero scale 4 mA output current with ± 0.1% offset error and a 20 mA full-scale output current with ± 0.2% gain error. The AD421 is available in a 16-lead, 0.3 inch-wide, plastic DIP and in a 16-lead, 0.3 inch-wide, SOIC package. The part is speci- fied over the industrial temperature range of –40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM REF IN REF OUT1 REF OUT2 (+2.5V) (+1.25V) (+2.5V) LV VCC AD421 112.5k⍀ 75k⍀ 134k⍀ BANDGAP REFERENCE 121k⍀ DATA CLOCK LATCH INPUT SHIFT REGISTER DAC LATCH POWER-ON RESET LOCAL OSCILLATOR 16-BIT SIGMA- DELTA DAC SWITCHED CURRENT SOURCES AND FILTERING 40⍀ 80k⍀ DRIVE COMP BOOST LOOP RTN COM C1 C2 C3 PRODUCT HIGHLIGHTS 1. The AD421 is a single chip, high performance, low cost solution for generating 4 mA to 20 mA signals for smart industrial control transmitters. 2. The AD421’s regulated supply voltage can be used to power any additional circuits in the transmitter. The regulated output value is pin selectable as either +3 V, +3.3 V or +5 V. 3. The AD421’s on-chip references can provide a precision reference voltage to other devices in the system. This refer- ence voltage can be either +1.25 V or +2.5 V. 4. The AD421 is fully compatible with standard HART cir- cuitry or other similar FSK protocols. 5. With the addition of a single discrete transistor, the AD421 can be operated from VCC + 2 V min to a maximum of the breakdown voltage of the pass transistor. 6. The AD421 converts the digital data to current with 16-bit resolution and monotonicity. Full-scale settling time to ± 0.1% typically occurs within 8 ms. 7. The AD421 features a programmable alarm current capabil- ity that allows the transmitter to send out of range currents to indicate a transducer fault. HART is a registered trademark of the HART Communication Foundation. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page Pin No. Mnemonic 1 REF OUT1 2 REF OUT2 3 REF IN 4 LV 5 LATCH 6 CLOCK 7 DATA 8 LOOP RTN 9 COM 10 C3 11 C2 12 C1 13 DRIVE 14 COMP 15 BOOST 16 VCC PIN FUNCTION DESCRIPTIONS AD421 Function Reference Output 1. A precision +1.25 V reference is provided at this pin. It is intended as a precision ref- erence source for other devices in the transmitter. REF OUT1 is a buffered output capable of providing up to 0.5 mA to external circuitry. If REF OUT 1 is required to sink current, a resistive load of 100 kΩ to COM should be added. (See Reference section.) Reference Output 2. A precision +2.5 V reference is provided at this pin. To operate the AD421 with its own reference, REF OUT2 should be connected to REF IN. It can also be used as a precision reference source for other devices in the transmitter. REF OUT2 is a buffered output capable of providing up to 0.5 mA to external circuitry. Voltage Reference Input. The reference voltage for the AD421 is applied to this pin and it sets the span for the AD421. The nominal reference voltage for the AD421 is +2.5 V for correct operation. This can be sup- plied using an external reference source or by using the part’s own REF OUT2 voltage. Regulated Voltage Control Input. The LV input controls the loop gain of the servo amplifier to set VCC. With LV connected to COM, the regulator voltage is set to 5 V nominal. If the LV input is connected through 0.01 µF to VCC, the regulated voltage is nominally 3.3 V. With LV connected to VCC the regulated voltage, VCC, is 3 V nominal. DAC Latch Input. Logic Input. A rising edge of the LATCH signal loads the data from the serial input shift register to the DAC latch and hence updates the output of the DAC. The number of clock cycles provided between latch pulses determines whether the DAC is in alarm or normal current mode. (See Digital Inter- face section.) Data Clock Input. Data on the DATA input is clocked into the shift register on the rising edge of this CLOCK input. The period of this clock equals the input serial data bit rate. This serial clock rate can be up to 10 MHz. If 16 clock cycles are provided between LATCH pulses then the data on the DATA input is accepted as normal 4–20 mA data. If more than 16 clock cycles are provided between LATCH pulses, the data is assumed to be alarm current data (see Digital Interface section). Data Input. The data to be loaded to the AD421 input shift register is applied to this input. Data should be valid on the rising edge of the CLOCK input. Loop Return Output. LOOP RTN is the return path for current flowing in the current loop. Common. This is the reference potential for the AD421 analog and digital inputs and outputs and for the voltage regulator output. Filtering Capacitor. A low dielectric absorption capacitor ceramic capacitor should be connected between this pin and COM for internal filtering of the switched current sources. Filtering Capacitor. See C3 description. Filtering Capacitor. See C3 description. Output from the Voltage Regulator Loop. The DRIVE signal controls the external pass transistor to establish and maintain the correct VCC level programmed by the LV inputs while providing the necessary bias as the loop cur- rent is programmed from 4 mA to 20 mA. Compensation Capacitor Input. A capacitor connected between COMP and DRIVE is required to stabilize the feedback loop formed with the regulator op amp and the external pass transistor. This open collector pin sinks the necessary current from the loop so that the current flowing into BOOST plus the current flowing into COM is equal to the programmed loop current. Power Supply. VCC is the power supply input of the AD421 and it also provides the voltage regulator output, driven by the external pass transistor. It is used both to bias the AD421 itself and to provide power for the rest of the smart transmitter circuitry. The LV input determines the regulated voltage output to be either 3 V, 3.3 V or 5 V nominal. Alternatively, a separate power supply can be connected to this pin to power the AD421. VCC should be decoupled to COM with a 2.2 µF capacitor. REV. C –5– 5 Page AD421 0.1␮F SENSORS RTD mV ⍀ TC AMBIENT TEMP SENSOR DVDD AVDD REF IN ANALOG TO DIGITAL CONVERTER AD7714/ AD7715 MCLK IN MCLK OUT CS DATA OUT SCLK DATA IN DGND AGND 3.3V 2.2␮F DN25D 0.01␮F 100k⍀ 4.7␮F VCC MICROCONTROLLER GND 1.25V 4.7␮F BOOST VCC REF OUT1 REF OUT2 REF IN CLOCK LATCH DATA AD421 LV 0.01␮F COMP DRIVE 1k⍀ 1000pF LOOP POWER COM C1 C2 C3 LOOP RTN Figure 14. AD421 in Smart Transmitter Application HART Interfacing The HART protocol uses a frequency shift (FSK) keying tech- nique based on the Bell 202 Communication Standard which is one of several standards used to transmit digital signals over the telephone lines. This technique is used to superimpose digital communication on to the 4 mA to 20 mA current loop connecting the central system to the transmitter in the field. Two different frequencies, 1200 Hz and 2200 Hz, are used to represent binary 1 and 0 respectively, as shown in Figure 15. These sine wave tones are superimposed on the dc signal at a low level with the average value of the sine wave signal being zero. This allows simultaneous analog and digital communica- tions. Additionally, no dc component is added to the existing 4 mA to 20 mA signal regardless of the digital data being sent over the line. Consequently, existing analog instruments con- tinue to work in systems that implement HART as the low-pass filtering usually present effectively removes the digital signal. A single pole 10 Hz low-pass filter effectively reduces the commu- nication signal to a ripple of about ± 0.01% of the full-scale signal. The HART protocol specifies that master devices like a host control system or a hand held terminal transmit a voltage signal whereas a slave or field device transmits a current signal. The current signal is converted into a corresponding voltage by the loop load resistor. APPROX +0.5mA APPROX –0.5mA 1200Hz “1” 2200Hz “0” Figure 15. HART Transmission of Digital Signals Figure 16 shows a block diagram of a smart and intelligent transmitter. An intelligent transmitter is a transmitter in which the functions of the microprocessor are shared between deriving the primary measurement signal, storing information regarding the transmitter itself, its application data and its location and also managing a communication system which enables two way communication to be superimposed on the same circuit that carries the measurement signal. A smart transmitter incorporat- ing the HART protocol is an example of a smart intelligent transmitter. MEMORY SENSORS A/D CONVERTER MICRO- PROCESSOR D/A CONVERTER COMMUNICATION SYSTEM 4mA TO 20mA MEASUREMENT CIRCUIT Figure 16. Smart and Intelligent Transmitter Figure 17 shows an example of the AD421 in a HART transmit- ter application. Most of the circuit is as outlined in the smart transmitter as shown in Figure 14. The HART data transmitted on the loop is received by the transmitter using a bandpass filter and modem and the HART data is transferred to the micro- controller’s UART or asynchronous serial port. HART data to be transmitted on the loop is sent from the microcontroller’s UART or asynchronous serial port to the modem. It is then waveshaped before being coupled onto the AD421’s output at the C3 pin. The value of the coupling capacitor CC is determined by the waveshaper output and the C3 capacitor of the AD421. The blocks containing the Bell 202 Modem, waveshaper and bandpass filter come in a complete solution with the 20C15 from Symbios Logic, Inc., or HT2012 from SMAR Research Corp. For a more complete AD421-20C15 interface, please refer to Application Note AN-534 on the Analog Devices’ website www.analog.com or contact your local sales office. REV. C –11– 11 Page

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