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PDF AD5262 Data sheet ( Hoja de datos )
| Número de pieza | AD5262 | |
| Descripción | 2-Channel/ 256-Position Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
256-Position, 2-Channel
Potentiometer Replacement
10 k⍀, 50 k⍀, 100 k⍀
Power Shut-Down, Less than 5 A
2.7 V to 5.5 V Single Supply
؎2.7 V Dual Supply
3-Wire SPI-Compatible Serial Data Input
Midscale Preset During Power-On
APPLICATIONS
Mechanical Potentiometer Replacement
Stereo Channel Audio Level Control
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Automotive Electronics Adjustment
2-Channel, 256-Position
Digital Potentiometer
AD5207
FUNCTIONAL BLOCK DIAGRAM
A1 W1 B1
A2 W2 B2
SHDN
VDD
VSS
CS
CLK
SDI
DGND
RDAC1 REGISTER
R
RDAC2 REGISTER
R
LOGIC
AD5207
POWER-
ON
RESET
8
SERIAL INPUT REGISTER
SDO
GENERAL DESCRIPTION
The AD5207 provides dual channel, 256-position, digitally
controlled variable resistor (VR) devices that perform the same
electronic adjustment function as a potentiometer or variable
resistor. Each channel of the AD5207 contains a fixed resistor with
a wiper contact that taps the fixed resistor value at a point
determined by a digital code loaded into the SPI-compatible
serial-input register. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the VR latch. The variable resistor
offers a completely programmable value of resistance, between
the A Terminal and the wiper or the B Terminal and the wiper.
The fixed A-to-B terminal resistance of 10 kΩ, 50 kΩ or 100 kΩ
has a ± 1% channel-to-channel matching tolerance with a nomi-
nal temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional switched
resistor designs and avoids any make-before-break or break-
before-make operation.
Each VR has its own VR latch, which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register, which is loaded from a standard
3-wire serial-input digital interface. Ten bits, to make up the
data word, are required and clocked into the serial input register.
The first two bits are address bits. The following eight bits are
the data bits that represent the 256 steps of the resistance value.
The reason for two address bits instead of one is to be compatible
with similar products such as AD8402 so that drop-in replacement
is possible. The address bit determines the corresponding VR
latch to be loaded with the data bits during the returned positive
edge of CS strobe. A serial data output pin at the opposite end
of the serial register allows simple daisy chaining in multiple
VR applications without additional external decoding logic.
An internal reset block will force the wiper to the midscale posi-
tion during every power-up condition. The SHDN pin forces an
open circuit on the A Terminal and at the same time shorts the
wiper to the B Terminal, achieving a microwatt power shutdown
state. When SHDN is returned to logic high, the previous latch
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface remains active during shutdown;
code changes can be made to produce new wiper positions when
the device is resumed from shutdown.
The AD5207 is available in 1.1 mm thin TSSOP-14 package,
which is suitable for PCMCIA applications. All parts are guaran-
teed to operate over the extended industrial temperature range
of –40°C to +125°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
Typical Performance Characteristics–AD5207
0.20
0.15
0.10
0.05
0.00
؊0.05
؊0.10
؊0.15
؊0.20
0
VDD = 5.5V, V SS = 0V
32 64 96 128 160 192 224
CODE – Decimal
TPC 1. 10 kΩ RDNL vs. Code
256
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
0
VDD = 5.5V, V SS = 0V
32 64 96 128 160 192 224 256
CODE – Decimal
TPC 4. 10 kΩ INL vs. Code
0.20
0.15
0.10
0.05
0.00
–0.05
–0.10
–0.15
–0.20
0
VDD = 5.5V, V SS = 0V
32 64 96 128 160 192 224 256
CODE – Decimal
TPC 2. 10 kΩ RINL vs. Code
1.0
IDD @ VDD/VSS = 5V/0V
0.1
IDD @ VDD/VSS = ؎2.5V
0.01
ISS @ VDD/VSS = ؎2.5V
IDD @ V DD/VSS = 3V/0V
0.001
0.0 1.0 2.0 3.0 4.0 5.0
VIH – V
TPC 5. Supply Current vs. Logic Input Voltage
0.3
VDD = 5.5V, V SS = 0V
0.2
0.1
0.0
–0.1
–0.2
–0.3
0
32 64 96 128 160 192 224 256
CODE – Decimal
TPC 3. 10 kΩ DNL vs. Code
20
VIL = VSS
18 VIH = VDD
16
14 VDD = 5.5V
12
10
8
VDD = 2.7V
6
4
2
0
–40 –20
0 20 40 60
TEMPERATURE – ؇C
80 100
TPC 6. Supply Current vs. Temperature
REV. 0
–5–
5 Page 
AD5207
Table IV.
D
(DEC)
255
128
1
0
RWB
(⍀)
10006
5045
84
45
Output State
Full-Scale (RAB – 1 LSB + RW)
Midscale
1 LSB
Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
45 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum current of no more
than 5 mA. Otherwise, degradation or possibly destruction of
the internal switch contacts can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and Terminal A also produces a
digitally controlled resistance RWA. When these terminals are used,
the B Terminal should be let open or tied to the wiper terminal.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch is
increased in value. The general equation for this operation is:
( )RWA
D
=
256 – D
256
×
RAB
+
RW
(2)
For example, when RAB = 10 kΩ, B terminal is either open or
tied to W, the following output resistance, RWA, will be set for
the following RDAC latch codes.
D
(DEC)
255
128
1
0
RWA
(⍀)
84
5045
10006
10045
Table V.
Output State
Full-Scale (RAB/256 + RW)
Midscale
1 LSB
Zero-Scale
The typical distribution of RAB from channel to channel matches
within ± 1%. Device-to-device matching is process-lot depen-
dent and is possible to have ± 30% variation. The change in RAB
with temperature has a 500 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage. Let’s ignore the effect of
the wiper resistance for the moment. For example, when con-
necting A Terminal to 5 V and B Terminal to ground, it produces
a programmable output voltage at the wiper starting at zero
volts up to 1 LSB less than 5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256
position of the potentiometer divider. Since AD5207 is capable
for dual supplies, the general equation defining the output volt-
age with respect to ground for any given input voltage applied to
terminals AB is:
( )VW
D
=
D
256
VA
+
256 − D
256
VB
(3)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent on the ratio of
RWA and RWB and not the absolute values; therefore, the drift
reduces to 15 ppm/°C. There is no voltage polarity constraint
between Terminals A, B, and W as long as the terminal voltage
stays within VSS < VTERM < VDD.
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Config-
ured as a potentiometer divider the –3 dB bandwidth of the
AD5207BRU10 (10 kΩ resistor) measures 600 kHz at half
scale. TPC 16 provides the large signal BODE plot characteris-
tics of the three available resistor versions 10 kΩ and 50 kΩ.
The gain flatness versus frequency graph, TPC 16, predicts
filter applications performance. A parasitic simulation model has
been developed and is shown in Figure 9. Listing I provides a
macro model net list for the 10 kΩ RDAC:
A
CA
CA = 45pF
RDAC
10k⍀
CW
70pF
B
CB
CB = 45pF
W
Figure 9. RDAC Circuit Simulation Model for RDAC = 10 kΩ
Listing I. Macro Model Net List for RDAC
.PARAM D=255, RDAC=10E3
*
.SUBCKT DPOT (A,W)
*
CA A 0 45E-12
RAW A W {(1-D/256)*RDAC+50}
CW W 0 70E-12
RBW W B {D/256*RDAC+50}
CB B 0 45E-12
*
.ENDS DPOT
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD5262.PDF ] | |
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