Datasheet.kr   

AD5341 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD5341은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AD5341 자료 제공

부품번호 AD5341 기능
기능 Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
제조업체 Analog Devices
로고 Analog Devices 로고


AD5341 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 28 페이지수

미리보기를 사용할 수 없습니다

AD5341 데이터시트, 핀배열, 회로
2.5 V to 5.5 V, 115 μA, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330/AD5331/AD5340/AD5341
FEATURES
GENERAL DESCRIPTION
AD5330: single 8-bit DAC in 20-lead TSSOP
AD5331: single 10-bit DAC in 20-lead TSSOP
AD5340: single 12-bit DAC in 24-lead TSSOP
AD5341: single 12-bit DAC in 20-lead TSSOP
Low power operation: 115 μA @ 3 V, 140 μA @ 5 V
Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Low power parallel data interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12-
bit DACs. They operate from a 2.5 V to 5.5 V supply consuming
just 115 μA at 3 V and feature a power-down mode that further
reduces the current to 80 nA. The devices incorporate an on-chip
output buffer that can drive the output to both supply rails, but
the AD5330, AD5340, and AD5341 allow a choice of buffered
or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel
interface. CS selects the device and data is loaded into the
input registers on the rising edge of WR.
The GAIN pin allows the output range to be set at 0 V to VREF or
0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in thin
shrink small outline packages (TSSOP).
1 Protected by U.S. Patent Number 5,969,657.
FUNCTIONAL BLOCK DIAGRAM
VREF
3
VDD
12
POWER-ON
RESET
AD5330
BUF 1
GAIN 8
DB.. 7 20
DB0 13
CS 6
WR 7
CLR 9
LDAC 10
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
4 VOUT
RESET
POWER-DOWN
LOGIC
Figure 1. AD5330
11 5
PD GND
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved.




AD5341 pdf, 반도체, 판매, 대치품
AD5330/AD5331/AD5340/AD5341
Parameter1
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
B Version2
Min Typ
Max Unit
2.5 5.5 V
140 250 μA
115 200 μA
0.2 1 μA
0.08 1 μA
Conditions/Comments
DACs active and excluding load currents. Unbuffered
Reference, VIH = VDD, VIL = GND
IDD increases by 50 μA at VREF > VDD − 100 mV.
In buffered mode, extra current is (5 + VREF/RDAC) μA,
where RDAC is the resistance of the resistor string.
1 See the Terminology section.
2 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095).
4 DC specifications tested with output unloaded.
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization, not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
Output Voltage Settling Time
AD5330
AD5331
AD5340
AD5341
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Multiplying Bandwidth
Total Harmonic Distortion
B Version3
Min Typ Max Unit Conditions/Comments
VREF = 2 V; see Figure 29
68
μs ¼ scale to ¾ scale change (0x40 to 0xC0)
79
μs ¼ scale to ¾ scale change (0x100 to 0x300)
8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00)
8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00)
0.7 V/μs
6 nV/s 1 LSB change around major carry
0.5 nV/s
200 kHz VREF = 2 V ± 0.1 V p-p; unbuffered mode
−70 dB VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
Rev. A | Page 4 of 28

4페이지










AD5341 전자부품, 판매, 대치품
AD5330/AD5331/AD5340/AD5341
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREF
3
VDD
12
POWER-ON
RESET
AD5330
BUF 1
GAIN 8
DB.. 7 20
DB0 13
CS 6
WR 7
CLR 9
LDAC 10
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
4 VOUT
RESET
POWER-DOWN
LOGIC
Figure 3. AD5330 Functional Block Diagram
11 5
PD GND
BUF 1
NC 2
VREF 3
VOUT 4
GND 5
CS 6
WR 7
GAIN 8
CLR 9
LDAC 10
8-BIT
AD5330
TOP VIEW
(Not to Scale)
20 DB7
19 DB6
18 DB5
17 DB4
16 DB3
15 DB2
14 DB1
13 DB0
12 VDD
11 PD
NC = NO CONNECT
Figure 4. AD5330 Pin Configuration
Table 5. AD5330 Pin Function Descriptions
Pin No. Mnemonic Description
1 BUF
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
2 NC
No Connect.
3 VREF
Reference Input.
4 VOUT
Output of DAC. Buffered output with rail-to-rail operation.
5 GND Ground reference point for all circuitry on the part.
6 CS
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7 WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
9 CLR
Asynchronous active low control input that clears all input registers and DAC registers to zero.
10 LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
11 PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12 VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20 DB0 to DB7 Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
Rev. A | Page 7 of 28

7페이지


구       성 총 28 페이지수
다운로드[ AD5341.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
AD534

Internally Trimmed Precision IC Multiplier

Analog Devices
Analog Devices
AD5340

Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

Analog Devices
Analog Devices

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵