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PDF AD558 Data sheet ( Hoja de datos )
| Número de pieza | AD558 | |
| Descripción | DACPORT Low Cost/ Complete uP-Compatible 8-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Complete 8-Bit DAC
Voltage Output–2 Calibrated Ranges
Internal Precision Bandgap Reference
Single-Supply Operation: +5 V to +15 V
Full Microprocessor Interface
Fast: 1 s Voltage Settling to ؎1/2 LSB
Low Power: 75 mW
No User Trims
Guaranteed Monotonic Over Temperature
All Errors Specified TMIN to TMAX
Small 16-Pin DIP and 20-Pin PLCC Packages
Single Laser-Wafer-Trimmed Chip for Hybrids
Low Cost
MIL-STD-883 Compliant Versions Available
DACPORT Low Cost, Complete
µP-Compatible 8-Bit DAC
AD558*
FUNCTIONAL BLOCK DIAGRAM
CONTROL
INPUTS
DIGITAL INPUT DATA (BUS)
GND CS CE LSB
MSB +VCC
I2L
CONTROL
LOGIC LSB
I2L LATCHES
MSB
8-BIT VOLTAGE-SWITCHING
D-TO-A CONVERTER
CONTROL
AMP
AD558
BAND -
GAP
REFERENCE
OUTPUT
AMP
VOUT
VOUTSENSE A
VOUTSELECT
GND
PRODUCT DESCRIPTION
The AD558 DACPORT® is a complete voltage-output 8-bit
digital-to-analog converter, including output amplifier, full
microprocessor interface and precision voltage reference on a
single monolithic chip. No external components or trims are
required to interface, with full accuracy, an 8-bit data bus to an
analog system.
The performance and versatility of the DACPORT is a result of
several recently-developed monolithic bipolar technologies. The
complete microprocessor interface and control logic is imple-
mented with integrated injection logic (I2L), an extremely dense
and low power logic structure that is process-compatible with
linear bipolar fabrication. The internal precision voltage reference
is the patented low voltage bandgap circuit which permits full-
accuracy performance on a single +5 V to +15 V power supply.
Thin-film silicon-chromium resistors provide the stability re-
quired for guaranteed monotonic operation over the entire oper-
ating temperature range (all grades), while recent advances in
laser-wafer-trimming of these thin-film resistors permit absolute
calibration at the factory to within ± 1 LSB; thus no user-trims
for gain or offset are required. A new circuit design provides
voltage settling to ± 1/2 LSB for a full-scale step in 800 ns.
The AD558 is available in four performance grades. The AD558J
and K are specified for use over the 0°C to +70°C temperature
range, while the AD558S and T grades are specified for –55°C
to +125°C operation. The “J” and “K” grades are available
either in 16-pin plastic (N) or hermetic ceramic (D) DIPS.
They are also available in 20-pin JEDEC standard PLCC pack-
ages. The “S” and “T” grades are available in the 16-pin her-
metic ceramic DIP package.
*Protected by U.S. Patent Nos. 3,887,863; 3,685,045; 4,323,795; Patents
Pending.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. The 8-bit I2L input register and fully microprocessor-
compatible control logic allow the AD558 to be directly
connected to 8- or 16-bit data buses and operated with
standard control signals. The latch may be disabled for
direct DAC interfacing.
2. The laser-trimmed on-chip SiCr thin-film resistors are
calibrated for absolute accuracy and linearity at the factory.
Therefore, no user trims are necessary for full rated accuracy
over the operating temperature range.
3. The inclusion of a precision low voltage bandgap reference
eliminates the need to specify and apply a separate refer-
ence source.
4. The voltage switching structure of the AD558 DAC section
along with a high speed output amplifier and laser trimmed
resistors give the user a choice of 0 V to +2.56 V or 0 V to
+10 V output ranges, selectable by pin-strapping. Circuitry is
internally compensated for minimum settling time on both
ranges; typically settling to ± 1/2 LSB for a full-scale 2.55 volt
step in 800 ns.
5. The AD558 is designed and specified to operate from a
single +4.5 V to +16.5 V power supply.
6. Low digital input currents, 100 µA max, minimize bus load-
ing. Input thresholds are TTL/low voltage CMOS compat-
ible over the entire operating VCC range.
7. All AD558 grades are available in chip form with guaranteed
specifications from +25°C to TMAX. MIL-STD-883, Class B
visual inspection is standard on Analog Devices bipolar
chips. Contact the factory for additional chip information.
8. The AD558 is available in versions compliant with MIL-
STD-883. Refer to Analog Devices Military Products Data-
book or current AD558/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
Applications–AD558
OUTPUT
AMP
16
40kΩ
2kΩ
15
14
14kΩ
13
500Ω
GND
VOUT
604Ω
Figure 4. 10.24 V Full-Scale Connection
NOTE: Decreasing the scale by putting a resistor in series with GND
will not work properly due to the code-dependent currents in GND.
Adjusting offset by injecting dc at GND is not recommended for the
same reason.
GROUNDING AND BYPASSING*
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the AD558 is intended for application in microcom-
puter systems where digital noise is prevalent, special care must
be taken to assure that its inherent precision is realized.
The AD558 has two ground (common) pins; this minimizes
ground drops and noise in the analog signal path. Figure 5
shows how the ground connections should be made.
OUTPUT
AMP
VOUT
16
VOUT SENSE
15
VOUT SELECT
14
(SEE NEXT
PAGE)
RL
GND
13
12
GND
11
+VCC
TO SYSTEM GND
TO SYSTEM GND
0.1µF (SEE TEXT)
TO SYSTEM VCC
The only consideration in selecting a supply voltage is that, in
order to be able to use the 0 V to 10 V output range, the power
supply voltage must be between +11.4 V and +16.5 V. If, how-
ever, the 0 V to 2.56 V range is to be used, power consumption
will be minimized by utilizing the lowest available supply voltage
(above +4.5 V).
TIMING AND CONTROL
The AD558 has data input latches that simplify interface to 8-
and 16-bit data buses. These latches are controlled by Chip
Enable (CE) and Chip Select (CS) inputs. CE and CS are inter-
nally “NORed” so that the latches transmit input data to the
DAC section when both CE and CS are at Logic “0”. If the ap-
plication does not involve a data bus, a “00” condition allows
for direct operation of the DAC. When either CE or CS go to
Logic “1”, the input data is latched into the registers and held
until both CE and CS return to “0”. (Unused CE or CS inputs
should be tied to ground.) The truth table is given in Table I.
The logic function is also shown in Figure 6.
Table I. AD558 Control Logic Truth Table
Latch
Input Data CE CS DAC Data Condition
0 0 0 0 “Transparent”
1 0 0 1 “Transparent”
0 g 0 0 Latching
1 g 0 1 Latching
0 0 g 0 Latching
1 0 g 1 Latching
X 1 X Previous Data Latched
X
X1
Previous Data Latched
NOTES
X = Does not matter.
g = Logic Threshold at Positive-Going Transition.
Figure 5. Recommended Grounding and Bypassing
It is often advisable to maintain separate analog and digital
grounds throughout a complete system, tying them common in
one place only. If the common tie-point is remote and acciden-
tal disconnection of that one common tie-point occurs due to
card removal with power on, a large differential voltage between
the two commons could develop. To protect devices that inter-
face to both digital and analog parts of the system, such as the
AD558, it is recommended that common ground tie-points
should be provided at each such device. If only one system
ground can be connected directly to the AD558, it is recom-
mended that analog common be selected.
POWER SUPPLY CONSIDERATIONS
The AD558 is designed to operate from a single positive power
supply voltage. Specified performance is achieved for any supply
voltage between +4.5 V and +16.5 V. This makes the AD558
ideal for battery-operated, portable, automotive or digital main-
frame applications.
*For additional insight, “An IC Amplifier Users’ Guide to Decoupling,
Grounding and Making Things Go Right For A change,” is available
at no charge from any Analog Devices Sales Office.
Figure 6. AD558 Control Logic Function
In a level-triggered latch such as that in the AD558 there is an
interaction between data setup and hold times and the width of
the enable pulse. In an effort to reduce the time required to test
all possible combinations in production, the AD558 is tested
with tDS = tW = 200 ns at 25°C and 270 ns at TMIN and TMAX,
with tDH = 10 ns at all temperatures. Failure to comply with
these specifications may result in data not being latched properly.
Figure 7 shows the timing for the data and control signals; CE
and CS are identical in timing as well as in function.
REV. A
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD558.PDF ] | |
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