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PDF AD574A Data sheet ( Hoja de datos )
| Número de pieza | AD574A | |
| Descripción | Complete 12-Bit A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Complete
12-Bit A/D Converter
FEATURES
Complete 12-Bit A/D Converter with Reference
and Clock
8- and 16-Bit Microprocessor Bus Interface
Guaranteed Linearity Over Temperature
0؇C to +70؇C – AD574AJ, K, L
–55؇C to +125؇C – AD574AS, T, U
No Missing Codes Over Temperature
35 s Maximum Conversion Time
Buried Zener Reference for Long-Term Stability
and Low Gain T.C. 10 ppm/؇C max AD574AL
12.5 ppm/؇C max AD574AU
Ceramic DIP, Plastic DIP or PLCC Package
Available in Higher Speed, Pinout-Compatible Versions
(15 s AD674B, 80 s AD774B; 10 s (with SHA) AD1674)
Available in Versions Compliant with MIL-STD-883 and
JAN QPL
AD574A*
BLOCK DIAGRAM AND
PIN CONFIGURATION
+5V SUPPLY
VLOGIC
1
28
STATUS
STS
DATA MODE SELECT 2
12/8
MSB
N
27
DB11
MSB
CHIP SELECT
CS
BYTE ADDRESS/
SHORT CYCLE
AO
3
4
CONTROL
I
3
B
B
S
T
L
E
26 DB10
25 DB9
READ/CONVERT 5
R/C
CLOCK
SAR
12 A A 24 DB8
T
CHIP ENABLE
CE
+12/+15V SUPPLY
VCC
+10V REFERENCE
REF OUT
ANALOG COMMON
AC
6
7
8
9
3k
10V
REF
COMP 12
IDAC
IDAC =
4 x N x IREF
EN
O
U
T
P
U
I
B
B
L
E
TB
B
23 DB7
22 DB6
21 DB5
20 DB4
DIGITAL
DATA
OUTPUTS
REFERENCE INPUT 10
REF IN
19.95k
-12/-15V SUPPLY
VEE
BIPOLAR OFFSET
BIP OFF
10V SPAN INPUT
10VIN
20V SPAN INPUT
20VIN
11
12
13
14
9.95k
5k
5k
IREF
DAC N
AD574A 12
8k
VEE
UN
FI
FB
EB
RL
SE
C
LSB
19 DB3
18 DB2
17 DB1
16
DB0
LSB
15
DIGITAL COMMON
DC
PRODUCT DESCRIPTION
The AD574A is a complete 12-bit successive-approximation
analog-to-digital converter with 3-state output buffer circuitry
for direct interface to an 8- or 16-bit microprocessor bus. A high
precision voltage reference and clock are included on-chip, and
the circuit guarantees full-rated performance without external
circuitry or clock signals.
The AD574A design is implemented using Analog Devices’
Bipolar/I2L process, and integrates all analog and digital func-
tions on one chip. Offset, linearity and scaling errors are mini-
mized by active laser-trimming of thin-film resistors at the wafer
stage. The voltage reference uses an implanted buried Zener for
low noise and low drift. On the digital side, I2L logic is used for
the successive-approximation register, control circuitry and
3-state output buffers.
The AD574A is available in six different grades. The AD574AJ,
K, and L grades are specified for operation over the 0°C to
+70°C temperature range. The AD574AS, T, and U are speci-
fied for the –55°C to +125°C range. All grades are available in a
28-pin hermetically-sealed ceramic DIP. Also, the J, K, and L
grades are available in a 28-pin plastic DIP and PLCC, and the
J and K grades are available in ceramic LCC.
The S, T, and U grades in ceramic DIP or LCC are available
with optional processing to MIL-STD-883C Class B; the T
and U grades are available as JAN QPL. The Analog Devices’
Military Products Databook should be consulted for details on
/883B testing of the AD574A.
*Protected by U.S. Patent Nos. 3,803,590; 4,213,806; 4,511,413; RE 28,633 .
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. The AD574A interfaces to most 8- or 16-bit microproces-
sors. Multiple-mode three-state output buffers connect di-
rectly to the data bus while the read and convert commands
are taken from the control bus. The 12 bits of output data
can be read either as one 12-bit word or as two 8-bit bytes
(one with 8 data bits, the other with 4 data bits and 4 trailing
zeros).
2. The precision, laser-trimmed scaling and bipolar offset resis-
tors provide four calibrated ranges: 0 volts to +10 volts and 0
volts to +20 volts unipolar, –5 volts to +5 volts and –10 volts
to +10 volts bipolar. Typical bipolar offset and full-scale cali-
bration errors of ± 0.1% can be trimmed to zero with one ex-
ternal component each.
3. The internal buried Zener reference is trimmed to 10.00
volts with 0.2% maximum error and 15 ppm/°C typical T.C.
The reference is available externally and can drive up to
1.5 mA beyond the requirements of the reference and bipolar
offset resistors.
4. AD674B (15 µs) and AD774B (8 µs) provide higher speed,
pin compatibility; AD1674 (10 µs) includes on-chip Sample-
Hold Amplifier (SHA).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD574A
THE AD574A OFFERS GUARANTEED MAXIMUM LINEARITY ERROR OVER THE FULL OPERATING
TEMPERATURE RANGE
DEFINITIONS OF SPECIFICATIONS
LINEARITY ERROR
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale”. The point
used as “zero” occurs 1/2 LSB (1.22 mV for 10 volt span) be-
fore the first code transition (all zeros to only the LSB “on”).
“Full scale” is defined as a level 1 1/2 LSB beyond the last code
transition (to all ones). The deviation of a code from the true
straight line is measured from the middle of each particular
code.
The AD574AK, L, T, and U grades are guaranteed for maxi-
mum nonlinearity of ± 1/2 LSB. For these grades, this means
that an analog value which falls exactly in the center of a given
code width will result in the correct digital output code. Values
nearer the upper or lower transition of the code width may pro-
duce the next upper or lower digital output code. The AD574AJ
and S grades are guaranteed to ± 1 LSB max error. For these
grades, an analog value which falls within a given code width
will result in either the correct code for that region or either
adjacent one.
Note that the linearity error is not user-adjustable.
DIFFERENTIAL LINEARITY ERROR (NO MISSING
CODES)
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing se-
quence as the analog input level is increased. Thus every code
must have a finite width. For the AD574AK, L, T, and U
grades, which guarantee no missing codes to 12-bit resolution,
all 4096 codes must be present over the entire operating tem-
perature ranges. The AD574AJ and S grades guarantee no miss-
ing codes to 11-bit resolution over temperature; this means that
all code combinations of the upper 11 bits must be present; in
practice very few of the 12-bit codes are missing.
UNIPOLAR OFFSET
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the actual
transition from that point. This offset can be adjusted as discussed
on the following two pages. The unipolar offset temperature
coefficient specifies the maximum change of the transition point
over temperature, with or without external adjustment.
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
QUANTIZATION UNCERTAINTY
Analog-to-digital converters exhibit an inherent quantization
uncertainty of ± 1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
LEFT-JUSTIFIED DATA
The data format used in the AD574A is left-justified. This
means that the data represents the analog input as a fraction of
4095
full-scale, ranging from 0 to 4096 . This implies a binary point
to the left of the MSB.
FULL-SCALE CALIBRATION ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10.000 volts full scale). The full-scale
calibration error is the deviation of the actual level at the last
transition from the ideal level. This error, which is typically
0.05% to 0.1% of full scale, can be trimmed out as shown in
Figures 3 and 4.
TEMPERATURE COEFFICIENTS
The temperature coefficients for full-scale calibration, unipolar
offset, and bipolar offset specify the maximum change from the
initial (25°C) value to the value at TMIN or TMAX.
POWER SUPPLY REJECTION
The standard specifications for the AD574A assume use of
+5.00 V and ± 15.00 V or ± 12.00 V supplies. The only effect of
power supply error on the performance of the device will be a
small change in the full-scale calibration. This will result in a
linear change in all lower order codes. The specifications show
the maximum full-scale change from the initial value with the
supplies at the various limits.
CODE WIDTH
A fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values
for which a given digital output code will occur. The nominal
value of a code width is equivalent to 1 least significant bit
(LSB) of the full-scale range or 2.44 mV out of 10 volts for a
12-bit ADC.
REV. B
–5–
5 Page 
Figure 15. Z80—AD574A Interface
AD574A
Note: Due to the large number of options that may be installed
in the PC, the I/O bus loading should be limited to one Schottky
TTL load. Therefore, a buffer/driver should be used when inter-
facing more than two AD574As to the I/O bus.
8086 Interface
The data mode select pin (12/8) of the AD574A should be con-
nected to VLOGIC to provide a 12-bit data output. To prevent
possible bus contention, a demultiplexed and buffered address/
data bus is recommended. In the cases where the 8-bit short
conversion cycle is not used, A0 should be tied to digital com-
mon. Figure 18 shows a typical 8086 configuration.
Figure 16. Wait State Generator
IBM PC Interface
The AD574A appears in Figure 17 interfaced to the 4 MHz
8088 processor of an IBM PC. Since the device resides in I/O
space, its address is decoded from only the lower ten address
lines and must be gated with AEN (active low) to mask out in-
ternal DMA cycles which use the same I/O address space. This
active low signal is applied to CS. IOR and IOW are used to
initiate the conversion and read, and are gated together to drive
the chip enable, CE. Because the data bus width is limited to
8 bits, the AD574A data resides in two adjacent addresses
selected by A0.
Figure 18. 8086—AD574A with Buffered Bus lnterface
For clock speeds greater than 4 MHz wait state insertion similar
to Figure 16 is recommended to ensure sufficient CE and R/C
pulse duration.
The AD574A can also be interfaced in a stand-alone mode (see
Figure 13). A low going pulse derived from the 8086’s WR sig-
nal logically ORed with a low address decode starts the conver-
sion. At the end of the conversion, STS clocks the data into the
three-state latches.
68000 Interface
The AD574, when configured in the stand-alone mode, will eas-
ily interface to the 4 MHz version of the 68000 microprocessor.
The 68000 R/W signal combined with a low address decode ini-
tiates conversion. The UDS or LDS signal, with the decoded
address, generates the DTACK input to the processor, latching
in the AD574A’s data. Figure 19 illustrates this configuration.
Figure 17. IBM PC—AD574A Interface
REV. B
–11–
Figure 19. 68000—AD574A Interface
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD574A.PDF ] | |
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