ACTS374DMSR Datasheet PDF - Intersil Corporation
| Part Number | ACTS374DMSR | |
| Description | Radiation Hardened Octal D Flip-Flop/ Three-State | |
| Manufacturers | Intersil Corporation | |
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ACTS374MS
April 1995
Radiation Hardened
Octal D Flip-Flop, Three-State
Features
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm2/mg
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2V Min
• Input Current ≤1µA at VOL, VOH
Description
The Intersil ATCS374MS is a radiation hardened octal D-type
flip-flop with three-state outputs. The eight edge-triggered flip-
flops enter data into their registers on the low to high transition of
clock (CP). The Output Enable (OEN) controls the three-state
outputs and is independent of the register operation. When OEN
is high, the outputs will be in the high impedance state.
The ACTS374MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD FINISH C
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
Ordering Information
PART NUMBER
ACTS374DMSR
ACTS374KMSR
ACTS374D/Sample
ACTS374K/Sample
ACTS374HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Truth Table
INPUTS
OUTPUTS
OE
L
L
L
H
H = High Level
L = Low Level
X = Immaterial
Q0
Z = High Impedance
CP Dn Qn
HH
LL
X X Q0
XXZ
= Transition from Low to High Level
= the level of Q before the indicated input conditions
were established
Functional Diagram
1 OF 8
FF
D DQ
CP
COMMON CONTROLS
CP
OE
Q
OE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number 518828
File Number 3998
|
| |
 
Specifications ACTS374MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
Interim Test 1 (Postburn-In)
100%/5004
1, 7, 9
Interim Test 2 (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Interim Test 3 (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A (Note 1)
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Group D
Sample/5005
1, 7, 9
NOTE:
1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005.
READ AND RECORD
ICC, IOL/H, IOZL/H
ICC, IOL/H, IOZL/H
ICC, IOL/H, IOZL/H
ICC, IOL/H, IOZL/H
Subgroups 1, 2, 3, 9, 10, 11
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUP METHOD
PRE RAD
Group E Subgroup 2
5005
1, 7, 9
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TEST
POST RAD
Table 4
READ AND RECORD
PRE RAD
POST RAD
1, 9 Table 4 (Note 1)
TABLE 8. BURN-IN TEST CONNECTIONS (+125oC < TA < 139oC)
OPEN
GROUND
STATIC BURN-IN 1 (Note 1)
- 1, 3, 4, 7, 8, 10, 11,
13, 14, 17, 18
STATIC BURN-IN 2 (Note 1)
- 10
DYNAMIC BURN-IN (Note 1)
-
1, 10
1/2 VCC = 3V ±0.5V
VCC = 6V ±0.5V
2, 5, 6, 9, 12, 15, 16, 19
20
2, 5, 6, 9, 12, 15, 16, 19 1, 3, 4, 7, 8, 11, 13,
14, 17, 18, 20
2, 5, 6, 9, 12, 15, 16, 19
20
NOTE:
1. Each pin except VCC and GND will have a series resistor of 500Ω ±5% for static burn-in.
OSCILLATOR
50kHz
25kHz
--
--
11 3, 4, 7, 8, 13,
14, 17, 18
TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25oC, ±5oC)
FUNCTION
OPEN
GROUND
VCC = 5V ±0.5V
Irradiation Circuit (Note 1)
2, 5, 6, 9, 12, 15, 16, 19
10 1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20
NOTE:
1. Each pin except VCC and GND will have a series resistor of 47kΩ ±5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.
Spec Number 518828
5
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