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AD10242 데이터시트 PDF




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부품번호 AD10242 기능
기능 40 MSPS MCM A/D Converter
제조업체 Analog Devices
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AD10242 데이터시트, 핀배열, 회로
a Dual, 12-Bit, 40 MSPS MCM A/D Converter
with Analog Input Signal Conditioning
AD10242
FEATURES
2 Matched ADCs with Input Signal Conditioning
Selectable Bipolar Input Voltage Range
(؎0.5 V, ؎1.0 V, ؎2.0 V)
Full MIL-STD-883B Compliant
80 dB Spurious-Free Dynamic Range
Trimmed Channel-Channel Matching
APPLICATIONS
Radar Processing
Communications Receivers
FLIR Processing
Secure Communications
Any I/Q Signal Processing Application
GENERAL DESCRIPTION
The AD10242 is a complete dual signal chain solution including
on-board amplifiers, references, ADCs, and output buffering
providing unsurpassed total system performance. Each channel is
laser trimmed for gain and offset matching and provides channel-
to-channel crosstalk performance better than 80 dB. The AD10242
utilizes two each of the AD9632, OP279, and AD9042 in a cus-
tom MCM to gain space, performance, and cost advantages over
solutions previously available.
The AD10242 operates with ± 5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion. Each channel is completely independent, allowing
operation with independent encode or analog inputs. The AD10242
also offers the user a choice of analog input signal ranges to mini-
mize additional signal conditioning required for multiple functions
within a single system. The heart of the AD10242 is the AD9042,
which is designed specifically for applications requiring wide
dynamic range.
The AD10242 is manufactured on Analog Devices’
MIL-PRF-38534 MCM line and is completely qualified. Units
are packaged in a custom, cofired, ceramic 68-lead gull wing
package and specified for operation from –55°C to +125°C.
Contact the factory for additional custom options including those
that allow the user to ac couple the ADC directly, bypassing the
front end amplifier section. Also see the AD9042 data sheet for
additional details on ADC performance.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 40 MSPS.
2. Dynamic performance specified over entire Nyquist band;
spurious signals @ 80 dBc for –1 dBFS input signals.
3. Low power dissipation: <2 W off ± 5.0 V supplies.
4. User defined input amplitude.
5. Packaged in 68-lead ceramic leaded chip carrier.
FUNCTIONAL BLOCK DIAGRAM
AIN3
AIN2
AIN1
UNEG UCOM UPOS
AIN3
AIN2
AIN1
UPOS
UCOM
UNEG
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
REV. D
OP279
AD9632
OP279
AD9632
OP279
AD9042
VREF
12
9
OUTPUT BUFFERING
TIMING
ENC ENC D9A D10A D11A
(MSB)
AD10242
OP279
AD9042
VREF
TIMING
12
OUTPUT BUFFERING
5
7
ENC
ENC
D11B (MSB)
D10B
D9B
D8B
D7B
D0B D1B D2B D3B D4B D5B D6B
(LSB)
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/461-3113
www.analog.com
© 2015 Analog Devices, Inc. All rights reserved.




AD10242 pdf, 반도체, 판매, 대치품
AD10242
Parameter
Temp
Test
Level
Mil
Subgroup
AD10242BZ/TZ
Min Typ Max
Unit
SPURIOUS-FREE DYNAMIC RANGE9
Analog Input @ 1.2 MHz
25°C
I
@ 4.85 MHz
25°C
I
4
Full II 5, 6
@ 9.9 MHz
25°C
I
4
Full II 5, 6
@ 19.5 MHz
25°C
I
4
Full II 5, 6
81
70 80
70 79
63 70
63 69
60 67
60 66
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
TWO-TONE IMD REJECTION10
F1, F2 @ –7 dBFS
Full II 4, 5, 6 70 76
dBc
CHANNEL-TO-CHANNEL ISOLATION11 25°C
IV 12
75 80
dB
TRANSIENT RESPONSE
25°C
V
10 ns
LINEARITY
Differential Nonlinearity
(Encode = 20 MHz)
Integral Nonlinearity
(Encode = 20 MHz)
25°C IV 12
Full IV 12
25°C
V
Full V
0.3 1.0 LSB
0.5 1.25 LSB
0.3 LSB
0.5 LSB
OVERVOLTAGE RECOVERY TIME12
VIN = 2.0 × FS
VIN = 4.0 × FS
DIGITAL OUTPUTS
Logic Compatibility
Logic “1” Voltage13
Logic “0” Voltage14
Output Coding
Full
Full
Full
Full
IV 12
IV 12
I 1, 2, 3
I 1, 2, 3
50 100 ns
75 200 ns
CMOS
3.5 4.2
0.45 0.65
Twos Complement
V
V
POWER SUPPLY
AVCC Supply Voltage
I (AVCC) Current
AVEE Supply Voltage
I (AVEE) Current
DVCC Supply Voltage
I (DVCC) Current
ICC (Total) Supply Current
Power Dissipation (Total)
Power Supply Rejection Ratio (PSRR)
Pass-Band Ripple to 10 MHz
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
V
VI
V
VI
V
I 1, 2, 3
I 1, 2, 3
I 7, 8
IV 12
5.0 V
260 mA
–5.0 V
55 mA
5.0 V
25 mA
350 400 mA
1.75 2.0 W
0.01 0.02 % FSR/% VS
0.2 dB
NOTES
1Gain tests are performed on AIN3 over specified input voltage range.
2Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance.
3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.
5ENCODE may also be driven differentially in conjunction with ENCODE; see Encoding the AD10242 section for details.
6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 40.0 MSPS.
8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS.
9Analog Input signal equals –1 dBFS; SFDR is the ratio of converter full scale to worst spur.
10Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz
± 100 kHz, 50 kHz f1 – f2 300 kHz.
11Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A IN1).
12Input driven to 2× and 4× AIN1 range for >4 clock cycles. Output recovers in band in specified time with Encode = 40 MSPS. No foldover guaranteed.
13Outputs are sourcing 10 µA.
14Outputs are sinking 10 µA.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
REV. D
–3–

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AD10242 전자부품, 판매, 대치품
AD10242
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve rated
performance; pulsewidth low is the minimum time that the
ENCODE pulse should be left in low state. At a given clock
rate, these specifications define an acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” deter-
mined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of the ENCODE
command and the time when all output data bits are within valid
logic levels.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power
supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR, without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. SFDR may be reported in
dBc (i.e., degrades as signal levels are lowered) or in dBFS
(always related back to converter full scale).
Transient Response
The time required for the converter to achieve 0.02% accu-
racy when a one-half full-scale step function is applied to the
analog input.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value of
the peak spurious component. The peak spurious component
may or may not be an IMD product. Two-tone SFDR may be
reported in dBc (i.e., degrades as signal levels are lowered) or
in dBFS (always related back to converter full scale).
–6– REV. D

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AD10242

40 MSPS MCM A/D Converter

Analog Devices
Analog Devices

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