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부품번호 | AD1315 기능 |
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기능 | High Speed Active Load with Inhibit Mode | ||
제조업체 | Analog Devices | ||
로고 | |||
전체 8 페이지수
a
FEATURES
+50 mA Voltage Programmable Current Range
1.5 ns Propagation Delay
Inhibit Mode Function
High Speed Differential Inputs for Maximum Flexibility
Hermetically Sealed Small Gull Wing Package
Compatible with AD1321, AD1324 Pin Drivers
APPLICATIONS
Automatic Test Equipment
Semiconductor Test System
Board Level Test System
High Speed Active Load
with Inhibit Mode
AD1315
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD1315 is a complete, high speed, current switching load
designed for use in linear, digital or mixed signal test systems.
By combining a high speed monolithic process with a unique
surface mount package, this product attains superb electrical
performance while preserving optimum packaging densities in
an ultrasmall 16-lead, hermetically sealed gull wing package.
Featuring current programmability of up to +50 mA, the
AD1315 is designed to force the device under test to source or
sink the programmed IOHPROG and IOLPROG currents. The IOH
and IOL currents are determined by applying a corresponding
voltage (5 V = 50 mA) to the IOH and IOL pins. The voltage-
to-current conversion is performed within the AD1315 thus
allowing the current levels to be set by a standard voltage out
digital-to-analog converter.
The AD1315’s transition from IOH to IOL occurs when the
output voltage of the device under test slews above or below the
programmed threshold, or commutation voltage. The commuta-
tion voltage is programmable from 2 V to +7 V, covering the
large spectrum of logic devices while able to support the large
current specifications (48 mA) typically associated with line
drivers. To test I/O devices, the active load can be switched into
a high impedance state (Inhibit mode) electrically removing the
active load from the path through the Inhibit mode feature. The
active load leakage current in Inhibit is typically 20 nA.
The Inhibit input circuitry is implemented utilizing high speed
differential inputs with a common-mode voltage range of 7 volts
and a maximum differential voltage of 4 volts. This allows for
the direct interface to the precision of differential ECL timing or
the simplicity of switching the Active Load from a single ended
TTL or CMOS logic source. With switching speeds from IOH
or Io~ into Inhibit of less than 1.5 ns, the AD1315 can be
electrically removed from the signal path “on-the-fly.”
The AD1315 is available in a 16-lead, hermetically sealed gull
wing package and is specified to operate over the ambient com-
mercial temperature range from 0°C to +70°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD1315
DEFINITION OF TERMS
Gain
The measured transconductance.
Gain = IOUT (@ 5V Input ) − IOUT (@ 0.2V Input )
V PROG(@ 5V ) − V PROG(@ 0.2V )
where:
VPROG values are measured at IOL/IOH PROG
Gain Error
The difference between the measured transconductance and the
ideal expressed as a % of full-scale range.
Ideal Gain = 10 mA/V
Gain Error = Ideal Gain − Actual Gain × 100
Ideal Gain
Offset Error
Offset Error is measured by setting the IOHPROG or IOLPROG
inputs to 0.2 V and measuring IOUT. Since both IOH and IOL
outputs are unipolar, this small initial offset of 2 mA must be set
to allow for measurement of possible negative offset. With a gain
of 10 mA/V, a 0.2 V input should yield an output of ± 2 mA. The
difference between the observed output and the ideal ± 2 mA
output is the offset error.
Offset Error = IOUT (@ 0.2 V) – Gain ϫ VPROG (@ 0.2 V)
Linearity Error
The deviation of the transfer function from a straight line de-
fined by Offset and Gain expressed as a % of FSR.
IOUT (calc) = Gain ϫ VPROG (@ set point) + Offset
where:
set point = VPROG (from 0.2 V to 5 V)
IOUT (FSR) = Gain ϫ VPROG (@ 5 V) + Offset
Linearity Error IOUT (measured ) − IOUT (calc) × 100
IOUT ( FSR )
Figure 1. Definition of Terms
Figure 2. Timing Diagram for Inhibit Transition
Figure 3. IOL, IOH Offset Current vs.
Temperature
Figure 4. IOL, IOH Gain Error vs.
Temperature
Figure 5. IOL, IOH Linearity Error vs.
Current Program Voltage
–4– REV. A
4페이지 AD1315
APPLICATIONS
The AD1315 has been optimized to function as an active load
in an ATE test system. Figure 14 shows a block diagram illus-
trating the electronics behind a single pin of a high speed digital
functional test system with the ability to test I/O pins on logic
devices. The AD1315 active load, AD1321 or AD1324 pin
driver, AD1317 high speed dual comparator and the AD664
quad 12-bit voltage DAC would comprise the pin electronic
portion of the test system. Such a system could operate at
100 MHz with the AD1321 (200 MHz with the AD1324) in a
data mode or 50 MHz (100 MHz) in the I/O mode.
The VCOM input sets the commutation voltage of the active load.
With DUT output voltage above VCOM, the load will sink cur-
rent (IOH). With DUT output voltage below VCOM, the load will
source current (IOL). Like the IOH and IOL return lines, the VCOM
must be able to sink or source 50 mA, therefore a standard op
amp will not suffice. An op amp with an external complemen-
tary output stage or a high power op amp such as the AD842
will work well here. A typical application is shown in Figure 15.
LAYOUT CONSIDERATIONS
IOHRTN and IOLRTN may be connected to any potential between
–2 V and +7 V. These return points must be able to source or
sink 50 mA, since the IOH and IOL programmed currents are
diverted here in the inhibit mode. The RTNs may be connected
to a suitable GND. However, to keep transient ground currents
to a minimum, they are typically tied to the VCOM programming
voltage point.
Figure 14. High Speed Digital Test System Block Diagram
REV. A
Figure 15. Suggested IOHRTN, IOLRTN, VCOM Hookup
–7–
7페이지 | |||
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