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AD1385 데이터시트 PDF




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부품번호 AD1385 기능
기능 16-Bit 500 kHz Wide Temperature Range Sampling ADC
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AD1385 데이터시트, 핀배열, 회로
a
FEATURES
16-Bit Resolution
500 kHz Sampling Rate
Differential Linearity Autocalibration
Specified over –55؇C to +125؇C Range
SNR 90 dB @ 100 kHz (min)
THD –88 dB @ 100 kHz (min)
0.0006% FSR DNL (typ)
0.0015% FSR INL (typ)
No Missing Codes
؎5, ؎10 V Bipolar Input Ranges
Zero Offset Autocalibration
APPLICATIONS
Medical Imaging
CAT
Magnetic Resonance
Radar
Vibration Analysis
Parametric Measurement Unit (ATE)
Digital Storage Oscilloscopes
Waveform Recorders
Analytical Instruments
16-Bit 500 kHz
Wide Temperature Range Sampling ADC
AD1385
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD1385 is a complete 500 kHz, 16-bit, sampling analog-
to-digital converter contained in a single package. Its differential
linearity autocalibration feature allows this high resolution, high
speed converter to offer outstanding noise and distortion perfor-
mance, as well as excellent INL and DNL specifications, over
the full military temperature range. Autocalibration effectively
eliminates DNL drift over temperature.
The AD1385 architecture includes a low noise, low distortion
track/hold, a three pass digitally corrected subranging ADC, and
linearity calibration circuitry. A complete linearity calibration
requires only 15 ms. Precision thin-film resistors and a propri-
etary DAC contribute to the part’s outstanding dynamic and
static performance.
The AD1385 uses four power supplies, ± 5 V and ± 15 V, and an
external 10 MHz clock. Power dissipation is nominally 2.76 W.
Two user selectable bipolar input ranges, ± 5 V and ± 10 V, are
provided. Careful attention to grounding and a single package
make it easy to design PCBs to achieve specified performance.
The AD1385’s pinout is nearly identical to that of the AD1382,
a factory calibrated 16-bit, 500 kHz SADC. Just two additional
connections, to enable and monitor autocalibration, are required.
This commonality provides an easy upgrade path to extend sys-
tem performance and operating temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD1385 pdf, 반도체, 판매, 대치품
AD1385
ABSOLUTE MAXIMUM RATINGS*
+VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V
VDD to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to +11 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Short Circuit Duration
Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
Track/Hold Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 sec
Digital Outputs . . . . . . . . . . . . . . 1 sec for Any One Output
Case Temperature (Operating) . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature
Range (Case)
Package Option*
AD1385KD
AD1385TD
AD1385TD/883B
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
*DH-48A = Bottom Brazed Ceramic DIP.
DH-48A
DH-48A
DH-48A
AD1385 PIN CONNECTIONS
The AD1385 is housed in a 48-pin bottom-brazed ceramic
bathtub package. The pinout is as follows:
Pin Function
Pin Function
11 CLOCK IN
12 POWER GROUND
48 VDD2 (+5 V POWER)
47 POWER GROUND
13 B1/B9 (MSB)
14 B2/B10
46 VSS2 (–5 V POWER)
45 AUTOZERO
15 B3/B11
44 B1 SELECT
16 B4/B12
43 POWER GROUND
17 B5/B13
42 POWER GROUND
18 B6/B14
41 CAL
19 B7/B15
40 GAIN ADJUST
10 B8/B16 (LSB)
39 +10 V REFERENCE OUT
11 VDD1 (+5 V SIGNAL)
12 POWER GROUND
38 –VS1 (–15 V)
37 SIGNAL GROUND
13 VSS1 (–5 V SIGNAL)
14 SIGNAL GROUND
36 +VS1 (+15 V)
35 SIGNAL GROUND
15 DATA STROBE
34 DNC
16 HI/LO BYTE SELECT 33 DNC
17 OE DATA ENABLE
32 +10 V REFERENCE IN
18 START CONVERT
31 VIN B
19 HOLD COMMAND OUT 30 VIN A
20 SIGNAL GROUND
29 OFFSET ADJUST
21 +VS2 (+15 V)
28 CAL STATUS
22 HOLD COMMAND IN 27 TRACK/HOLD OUTPUT
23 –VS2 (–15 V)
24 POWER GROUND
26 SIGNAL GROUND
25 TRACK/HOLD INPUT
DNC = DO NOT CONNECT.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1385 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. 0

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AD1385 전자부품, 판매, 대치품
AD1385
Figure 13. AD1385 Functional Block Diagram
THEORY OF OPERATION
The AD1385 performs conversions using a three-pass subrang-
ing technique. This proven circuit concept, implemented with
state of the art components, allows the ADC, track-hold, and a
low noise reference to fit into a single hermetic package, simpli-
fying the task of board design. The T/H and ADC portions of
the AD1385 are distinct circuits with inputs and outputs avail-
able on separate pins. This functional division allows greatest
application flexibility. The AD1385’s major functional blocks
are shown in Figure 13.
The T/H uses a low noise high performance hybrid amplifier and
high speed analog switches to achieve precision performance. It
operates as an inverting amplifier during Track mode. Summing
junction switch S1 disconnects the analog input to place the cir-
cuit into Hold mode; the amplifier’s output stays constant because
the dc path to its inverting input is broken. S1 also grounds the
junction of R1 and R2 to minimize signal feedthrough. Pedestal
is independent of the analog input level because all switching
is done near ground. This ensures very low nonlinearity and
distortion.
A precision Reference DAC and an 8-bit flash ADC form the
heart of the AD1385’s subranging design. High speed amplifiers
combine the analog input and DAC output to produce the volt-
ages encoded by the flash ADC during each pass. A logic array
provides all necessary timing, control, and computation.
The first rising clock edge after Start Convert goes high begins
the conversion (provided the previous conversion is complete).
The Hold Command goes high and switches the T/H into hold.
The held signal from the T/H goes through S2, S3, and Error
Amp 2 to the flash ADC. During this pass Error Amp 2 actually
attenuates the ADC input to keep the voltage within the flash
ADC’s input range. The flash ADC is strobed after a 100 ns
settling period. The 8-bit result is saved in the logic array and is
routed to the MSBs of the Reference DAC.
Error Amp 1 amplifies the difference between the Reference
DAC output and the held input signal during the second pass.
S4 routes this error signal to the flash ADC, which is strobed a
second time after Error Amp 1 has settled. The new 8-bit result
is used to correct the previous result, increasing the accuracy of
this intermediate answer to 13-bit precision. Following this the
Reference DAC is updated.
Both error amplifiers are active during the third pass. S2 is
closed, allowing Error Amp 2 to amplify Error Amp 1’s output.
S3 now brings Error Amp 2’s output to the flash ADC. The
flash ADC is strobed a final time after the DAC and both error
amplifiers have settled. The logic array combines the data from
the third flash conversion with the earlier 13-bit word to pro-
duce the final 16-bit result. The T/H is returned to track mode,
and Error Amp 2 is reconnected as an attenuator 50 ns after the
completion of the third flash conversion to prepare for the next
conversion.
The output data are placed on the data bus in two 8-bit bytes
to be read by the host system. The Data Strobe output synchro-
nizes the data transfer by providing a rising edge for the first
byte and a falling edge for the second byte. The Hi/Lo Byte
Select input allows the user to choose which data byte is pre-
sented first. B1 Select sets the polarity of the MSB to provide
either complementary twos complement or complementary off-
set binary data.
The AD1385’s internal linearity calibration capability may be
used to compensate for shifts in Reference DAC linearity with
time and temperature. The calibration sequence uses the
AD1385’s error amplifiers and flash converter to directly mea-
sure Reference DAC linearity errors. The routine calculates the
Corrections required to each of the Reference DAC’s 8 MSBs
and stores these in an internal memory; the memory address is
determined by the Reference DAC’s codes. The RAM data con-
trol a Correction DAC whose output is summed with the Refer-
ence DAC’s output. Together the two DACs provide the 18-bit
linearity required for accurate A/D conversions. Calibration
corrects only linearity errors, and has a negligible effect on
gain and offset errors. A calibration cycle requires 15 ms and
may be initiated at any time (see Autozero).
REV. 0
–7–

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