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PDF AD1812 Data sheet ( Hoja de datos )
| Número de pieza | AD1812 | |
| Descripción | SoundPort Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD1812 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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a
SoundPort Controller
AD1812
FEATURES
Compatibility with:
Sound Blaster Pro*
AdLib*
Windows* Sound System
16-Bit ⌺⌬ Stereo Codec
MPC Level-2+ Mixer
Dual DMA/Full Duplex Operation
On-Chip FIFO Buffers
Sample Rates from 5.5 kHz to 50 kHz
ADPCM Compression/Decompression
Plug and Play Compliant
Compatible MIDI MPU-401 Port
Integrated Game Port
Free Supporting Software:
Windows 3.1 Driver
Windows 95 Driver
Control Applets
Diagnostics
Power Management Modes
Operation from +5 V Supply
16-Bit Parallel Interface to ISA Bus
24 mA Bus Drive Capability
*Sound Blaster Pro is a trademark of Creative Labs, Ltd.
*AdLib is a trademark of AdLib Multimedia.
*Windows is a trademark and Microsoft is a registered trademark of
*Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
PRODUCT OVERVIEW
The AD1812 SoundPort® Controller is a single chip audio sub-
system for adding 16-bit stereo audio to personal computers.
The AD1812 is compatible with Sound Blaster Pro, AdLib, and
the Microsoft* Windows Sound System. The AD1812 provides
an integrated audio solution for enhanced business audio, enter-
tainment sound effects, and multimedia applications.
The AD1812 audio subsystem combines an integrated digital
audio controller, a powerful signal processor, a mixer, and a
16-bit Σ∆ stereo codec. The DOS games register set, the Win-
dows Sound System register set, music synthesis hardware, an
MPU-401 compatible UART interface, a game port (with
timer), and a Plug and Play ISA interface are all contained on
chip. The on-chip Plug and Play (PnP) routine provides con-
figuration services for the internal logical devices and an exter-
nal modem chipset.
The AD1812 can record compress and playback voice, sound
and music. The system provides all PC 95 audio conversion and
compatibility requirements for a multimedia enabled PC.
(continued on Page 12)
FUNCTIONAL BLOCK DIAGRAM
XTALI / O
A_1 B_1 A_X B_X A_2 B_2 A_Y B_Y MIDI _IN MIDI _OUT
M IC
LINE
AUX1
L_OUT
MONO I/O
R_OUT
MONO_IN
AUX2
DACIN
DACOUT
AD1812
0dB/
20dB
OSCILLATORS
JOYSTICK/GAME PORT INTERFACE
MPU-401 UART
MΣ
PGA
Σ ∆ A/D
CONVERTER
FORMAT FIFO
GGG
MMM
ΣΣΣ
ΣΣ
GG
MM
Σ
DIGITAL MIX
ATTENUATE
ATTN/
MUTE
Σ ∆ D/A
CONVERTER
Σ
Σ
FORMAT
FIFO
G = GAIN/AMPLIFIER BLOCK
M = MUTE BLOCK
ROM
RAM
GAME
REGISTER
SET
&
WSS
REGISTER
SET
ATTN
Σ ∆ D/A
CONVERTER
ADSP-2171
PARALLEL
BUS
INTERFACE
CONTROL
REGISTERS
PLUG
AND
PLAY
REGISTERS
MODEM_IRQ
MODEM_SEL
DRQ (0, 1, 3, 5, 6, 7)
IRQ (3, 4, 5, 7, 9, 10, 11, 12)
PC_D (15:0)
PC_A (15:0)
AEN
DACK (0, 1, 3, 5, 6, 7)
IOR
IOW
SBHE
IO_CH16
PWRDWN
PnP
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD1812
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min Typ
Max
Units
IOW/IOR Strobe Width
IOW/IOR Rising to IOW/IOR Falling
Write Data Setup to IOW Rising
IOR Falling to Valid Read Data
AEN Setup to IOW/IOR Falling
AEN Hold from IOW/IOR Rising
Adr Setup to IOW/IOR Falling
Adr Hold from IOW/IOR Rising
DACK Rising to IOW/IOR Falling
IOW/IOR Rising to DACK Falling
DACK Setup to IOW/IOR Falling
Data Hold from IOR Rising
Data Hold from IOW Rising
DRQ Hold from IOW/IOR Falling
DACK Hold from IOW Rising
DACK Hold from IOR Rising
tSTW
tBWDN
tWDSU
tRDDV
tAESU
tAEHD
tADSU
tADHD
tDKSU1
tDKHD1
tDKSU2
tDHD1
tDHD2
tDRHD
tDKHD2
tDKHD3
100
80
10
10
0
10
10
20
0
10
15
10
10
ns
ns
ns
40 ns
ns
ns
ns
ns
ns
ns
ns
20 ns
ns
25 ns
ns
ns
*Guaranteed, not tested.
Specifications subject to change without notice.
General Notes
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield
meaningful results for an additional device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add
up parameters to derive longer times. Note that all 8-bit DMA transfers occur on channels 0, 1, and 3, while all 16-bit DMA transfers occur on channels 5, 6, and 7.
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOR
PC_D (7:0) /
PC_D (15:0)
PC_A (15:0)
tDKSU1
tAESU
tDKHD1
tAEHD
tSTW
tADSU
tRDDV
tDHD1
tADHD
Figure 1. PIO Read Cycle
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOR
PC_D (7:0) /
PC_D (15:0)
tDKSU2
tAESU
tDRHD
tSTW
tRDDV
tDKHD3
tAEHD
tDHD1
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOW
PC_D (7:0) /
PC_D (15:0)
PC_A (15:0)
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOW
PC_D (7:0) /
PC_D (15:0)
tDKSU1
tAESU
tADSU
tSTW
tWDSU
tDKHD1
tAEHD
tDHD2
tADHD
Figure 2. PIO Write Cycle
tDKSU2
tAESU
tDRHD
tSTW
tWDSU
tDKHD2
tAEHD
tDHD2
Figure 3. DMA Read Cycle
Figure 4. DMA Write Cycle
REV. 0
–5–
5 Page 
Modem Interface Signals
Pin Name
P/TQFP
MODEM_IRQ
38
MODEM_EN
39
MODEM_SEL
118
AD1812
I/O Description
I Modem IRQ. The external modem asserts this pin HI to indicate a pending inter-
rupt. The AD1812 converts this signal to the appropriate interrupt in either Plug
and Play (LDN = 5) or Non-Plug and Play mode.
I Modem Enable. When this pin is asserted (HI), the AD1812 enables the logical
device (LDN = 5) for an external modem chipset. Otherwise, LDN = 5 does not
exist. The state of this pin should not be altered after reset.
O Modem Select. This active LO pin is a chip select for an external modem chipset.
The AD1812 decodes the (Plug & Play or Non-Plug and Play) configured ISA
bus address. AEN must be LO before asserting the MODEM_SEL pin.
Game Port
Pin Name
A_1
A_2
A_X
A_Y
B_1
B_2
B_X
B_Y
P/TQFP
41
42
46
47
43
44
48
49
I/O Description
I Game Port A, Button #1.
I Game Port A, Button #2.
I Game Port A X-Axis.
I Game Port A Y-Axis.
I Game Port B, Button #1.
I Game Port B, Button #2.
I Game Port B X-Axis.
I Game Port B Y-Axis.
MIDI Interface Signals
Pin Name
P/TQFP
MIDI_IN
MIDI_OUT
31
96
I/O Description
I RXD MIDI Input.
O TXD MIDI Output.
Miscellaneous
Pin Name
PNP
XTALO
XTALI
PWRDWN
VREF_X
VREF
L_FILT
R_FILT
XCTL0
XCTL1
GVC
NC
P/TQFP
37
I/O
I
30
29
36
60
59
54
53
95
159
40
1–4, 81, 120–125,
156–158, 160
O
I
I
O
I
I
I
O
O
I
Description
Plug and Play Select. When this pin is asserted (HI), the Plug and Play
mode is enabled. If PnP is LO, the AD1812 operates in legacy mode, and
the Plug and Play configuration is disabled.
14.31818 MHz Crystal Output.
14.31818 MHz Clock Input, can be OSC from the ISA bus.
Power Down Signal. Active LO.
Voltage Reference.
Voltage Reference Filter.
Left Channel Filter Input.
Right Channel Filter Input.
External Control 0. The state of this pin (TTL HI or LO) is reflected in
codec indexed register 0x0A, Bit 6.
External Control 1. The state of this pin (TTL HI or LO) is reflected in
codec indexed register 0x0A, Bit 7.
Game Port Voltage Capacitor.
No Connect.
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD1812.PDF ] | |
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