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AD1812 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD1812은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AD1812 자료 제공

부품번호 AD1812 기능
기능 SoundPort Controller
제조업체 Analog Devices
로고 Analog Devices 로고


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AD1812 데이터시트, 핀배열, 회로
a
SoundPort Controller
AD1812
FEATURES
Compatibility with:
Sound Blaster Pro*
AdLib*
Windows* Sound System
16-Bit ⌺⌬ Stereo Codec
MPC Level-2+ Mixer
Dual DMA/Full Duplex Operation
On-Chip FIFO Buffers
Sample Rates from 5.5 kHz to 50 kHz
ADPCM Compression/Decompression
Plug and Play Compliant
Compatible MIDI MPU-401 Port
Integrated Game Port
Free Supporting Software:
Windows 3.1 Driver
Windows 95 Driver
Control Applets
Diagnostics
Power Management Modes
Operation from +5 V Supply
16-Bit Parallel Interface to ISA Bus
24 mA Bus Drive Capability
*Sound Blaster Pro is a trademark of Creative Labs, Ltd.
*AdLib is a trademark of AdLib Multimedia.
*Windows is a trademark and Microsoft is a registered trademark of
*Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
PRODUCT OVERVIEW
The AD1812 SoundPort® Controller is a single chip audio sub-
system for adding 16-bit stereo audio to personal computers.
The AD1812 is compatible with Sound Blaster Pro, AdLib, and
the Microsoft* Windows Sound System. The AD1812 provides
an integrated audio solution for enhanced business audio, enter-
tainment sound effects, and multimedia applications.
The AD1812 audio subsystem combines an integrated digital
audio controller, a powerful signal processor, a mixer, and a
16-bit Σ∆ stereo codec. The DOS games register set, the Win-
dows Sound System register set, music synthesis hardware, an
MPU-401 compatible UART interface, a game port (with
timer), and a Plug and Play ISA interface are all contained on
chip. The on-chip Plug and Play (PnP) routine provides con-
figuration services for the internal logical devices and an exter-
nal modem chipset.
The AD1812 can record compress and playback voice, sound
and music. The system provides all PC 95 audio conversion and
compatibility requirements for a multimedia enabled PC.
(continued on Page 12)
FUNCTIONAL BLOCK DIAGRAM
XTALI / O
A_1 B_1 A_X B_X A_2 B_2 A_Y B_Y MIDI _IN MIDI _OUT
M IC
LINE
AUX1
L_OUT
MONO I/O
R_OUT
MONO_IN
AUX2
DACIN
DACOUT
AD1812
0dB/
20dB
OSCILLATORS
JOYSTICK/GAME PORT INTERFACE
MPU-401 UART
MΣ
PGA
Σ ∆ A/D
CONVERTER
FORMAT FIFO
GGG
MMM
ΣΣΣ
ΣΣ
GG
MM
Σ
DIGITAL MIX
ATTENUATE
ATTN/
MUTE
Σ ∆ D/A
CONVERTER
Σ
Σ
FORMAT
FIFO
G = GAIN/AMPLIFIER BLOCK
M = MUTE BLOCK
ROM
RAM
GAME
REGISTER
SET
&
WSS
REGISTER
SET
ATTN
Σ ∆ D/A
CONVERTER
ADSP-2171
PARALLEL
BUS
INTERFACE
CONTROL
REGISTERS
PLUG
AND
PLAY
REGISTERS
MODEM_IRQ
MODEM_SEL
DRQ (0, 1, 3, 5, 6, 7)
IRQ (3, 4, 5, 7, 9, 10, 11, 12)
PC_D (15:0)
PC_A (15:0)
AEN
DACK (0, 1, 3, 5, 6, 7)
IOR
IOW
SBHE
IO_CH16
PWRDWN
PnP
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD1812 pdf, 반도체, 판매, 대치품
AD1812
ANALOG OUTPUT
Parameter
Full-Scale Output Voltage
OL = 0
OL = 1
Output Impedance*
External Load Impedance
Output Capacitance*
External Load Capacitance
VREF
VREF Output Impedance
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)*
SYSTEM SPECIFICATIONS
Parameter
System Frequency Response Ripple* (Line In to Line Out)
Differential Nonlinearity*
Phase Linearity Deviation*
STATIC DIGITAL SPECIFICATIONS
Parameter
High-Level Input Voltage (VIH): Digital Inputs
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH), IOH = 24 mA
Low-Level Output Voltage (VOL), IOL = 24 mA
Input Leakage Current
Output Leakage Current
POWER SUPPLY
Parameter
Power Supply Range—Analog
Power Supply Range—Digital
Power Supply Current
Power Dissipation
Analog Supply Current
Digital Supply Current
Digital Power Supply Current—Power Down
Analog Power Supply Current—Power Down
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS*
Parameter
Input Clock Frequency
Recommended Clock Duty Cycle
Power Up Initialization Time
*Guaranteed not tested.
Specifications subject to change without notice.
Min
1.8
2.5
10
2.05
Min
Min
2
2.4
–10
–10
Min
4.75
4.75
40
Min
6
10
Typ Max
2.0 2.2
2.8 3.11
600
15
100
2.25 2.45
4
±5
Typ Max
1.0
±1
5
Typ Max
0.8
0.4
10
10
Typ Max
5.25
5.25
250
1.25
55
195
15
1
Typ
14.31818
50
Max
18
90
500
Units
V p-p
V p-p
k
pF
pF
V
k
mV
Units
dB
LSB
Degrees
Units
V
V
V
V
µA
µA
Units
V
V
mA
W
mA
mA
mA
mA
dB
Units
MHz
%
ms
–4– REV. 0

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AD1812 전자부품, 판매, 대치품
AD1812
Table II. Codec Transfer 16-Bit Interface with Byte Swap (P/CINF8 = 0, P/CBSW = 1)*
Format
Word 1 (16-Bit)
MSB
LSB
Word 0 (16-Bit)
MSB
LSB
Mono, 16-Bit
Little Endian
Lower 8 Bits of
Sample 1
Left Channel
Upper 8 Bits of
Sample 1
Left Channel
Lower 8 Bits of
Sample 0
Left Channel
Upper 8 Bits of
Sample 0
Left Channel
Stereo, 16-Bit
Little Endian
Lower 8 Bits of
Sample 0
Right Channel
Upper 8 Bits of
Sample 0
Right Channel
Lower 8 Bits of
Sample 0
Left Channel
Upper 8 Bits of
Sample 0
Left Channel
Mono, 8-Bit
Linear PCM
-Law PCM
A-Law PCM
Sample 2, 8 Bits
Left Channel
Sample 3, 8 Bits
Left Channel
Sample 0, 8 Bits
Left Channel
Sample 1, 8 Bits
Left Channel
Stereo, 8-Bit
Linear PCM
-Law PCM
A-Law PCM
Sample 1, 8 Bits
Left Channel
Sample 1, 8 Bits
Right Channel
Sample 0, 8 Bits
Left Channel
Sample 0, 8 Bits
Right Channel
Mono, 4-Bit
IMA-ADPCM
Sample 5,
4 Bits
Left
Channel
Sample 4,
4 Bits
Left
Channel
Sample 7,
4 Bits
Left
Channel
Sample 6,
4 Bits
Left
Channel
Sample 1,
4 Bits
Left
Channel
Sample 0,
4 Bits
Left
Channel
Sample 3,
4 Bits
Left
Channel
Sample 2,
4 Bits
Left
Channel
Stereo, 4-Bit
IMA-ADPCM
Sample 2,
4 Bits
Right
Channel
Sample 2,
4 Bits
Left
Channel
Sample 3,
4 Bits
Right
Channel
Sample 3,
4 Bits
Left
Channel
Sample 0,
4 Bits
Right
Channel
Sample 0,
4 Bits
Left
Channel
Sample 1,
4 Bits
Right
Channel
Sample 1,
4 Bits
Left
Channel
Mono, 16-Bit
Big Endian
Upper 8 Bits of
Sample 1
Left Channel
Lower 8 Bits of
Sample 1
Left Channel
Upper 8 Bits of
Sample 0
Left Channel
Lower 8 Bits of
Sample 0
Left Channel
Stereo, 16-Bit
Big Endian
Upper 8 Bits of
Sample 0
Right Channel
Lower 8 Bits of
Sample 0
Right Channel
Upper 8 Bits of
Sample 0
Left Channel
Lower 8 Bits of
Sample 0
Left Channel
*Regardless of the data format used, the AD1812’s codec always transfers 32 bits of data (two 16-bit words).
IOR/IOW
DATA (15:0)
tSTW
tBWDN
tSTW
WORD 0
WORD 1
Figure 6. Codec Transfers 16-Bit Interface
REV. 0
–7–

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