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AD1835 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD1835은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AD1835 자료 제공

부품번호 AD1835 기능
기능 2 ADC/ 8 DAC/ 96 kHz/ 24-Bit Codec
제조업체 Analog Devices
로고 Analog Devices 로고


AD1835 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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AD1835 데이터시트, 핀배열, 회로
PRELIMINARY TECHNICAL DATA
a
2 ADC, 8 DAC,
96 kHz, 24-Bit -Codec
Preliminary Technical Data
AD1835
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on One DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit Sigma-Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –92 dB THD + N, 100 dB SNR,
and Dynamic Range
DACs: –95 dB THD + N, 110 dB SNR,
and Dynamic Range
On-Chip Volume Controls per Channel with
1024-Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-Emphasis Processing
Supports 256 ؋ fS, 512 ؋ fS, and 768 ؋ fS Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARCSPORT
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1835 is a high-performance, single-chip codec featuring
four stereo DACs and one stereo ADC. Each DAC comprises a
high-performance digital interpolation filter, a multibit sigma-
delta modulator featuring Analog Devices’ patented technology,
(Continued on Page 11 )
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT MCLK PD/RST M/S AVDD AVDD
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ADCLP
ADCLN
ADCRP
ADCRN
-
ADC
-
ADC
SERIAL DATA
I/O PORT
DIGITAL
FILTER
DIGITAL
FILTER
CONTROL PORT
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
CLOCK
DIGITAL
FILTER
DIGITAL
FILTER
DIGITAL
FILTER
DIGITAL
FILTER
DGND DGND AGND AGND AGND AGND
-
DAC
-
DAC
-
DAC
-
DAC
VREF
OUTLP1
OUTLN1
OUTRP1
OUTRN1
OUTLP2
OUTLN2
OUTRP2
OUTRN2
OUTLP3
OUTLN3
OUTRP3
OUTRN3
OUTLP4
OUTLN4
OUTRP4
OUTRN4
FILTD
FILTR
SHARC is a registered trademark of Analog Devices, Inc.
REV. PrA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002




AD1835 pdf, 반도체, 판매, 대치품
PRELIMINARY TECHNICAL DATA
AD1835–SPECIFICATIONS
TIMING
Parameter
MASTER CLOCK AND RESET
tMH MCLK High
tML MCLK Low
tPDR PD/RST Low
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCOE
tCOD
tCOTS
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
DAC SERIAL PORT
Normal Mode (Slave)
tDBH
DBCLK High
tDBL DBCLK Low
fDB DBCLK Frequency
tDLS DLRCLK Setup
tDLH DLRCLK Hold
tDDS DSDATA Setup
tDDH
DSDATA Hold
Packed 256 Modes (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ADC SERIAL PORT
Normal Mode (Master)
tABD ABCLK Delay
tALD ALRCLK Delay Low
tABDD
ASDATA Delay
Normal Mode (Slave)
tABH ABCLK High
tABL ABCLK Low
fAB ABCLK Frequency
tALS ALRCLK Setup
tALH ALRCLK Hold
Packed 256 Mode (Master)
tPABD
tPALD
tPABDD
ABCLK Delay
LRCLK Delay
ASDATA Delay
Min Max
15
15
20
40
40
80
10
10
10
10
15
20
25
60
60
64 ϫ fS
10
10
10
10
15
15
256 ϫ fS
10
5
10
10
60
60
64 ϫ fS
5
15
25
5
10
20
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Rising
From CLATCH Falling
From CCLK Falling
From CLATCH Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
To ABCLK Rising
From ABCLK Rising
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
–4– REV. PrA

4페이지










AD1835 전자부품, 판매, 대치품
PRELIMINARY TECHNICAL DATA
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
DVDD 1
CLATCH 2
CIN 3
PD/RST 4
AGND 5
OUTLN1 6
OUTLP1 7
OUTRN1 8
OUTRP1 9
AGND 10
AVDD 11
OUTLN2 12
OUTLP2 13
AD1835
TOP VIEW
(Not to Scale)
39 DVDD
38 DBCLK
37 DLRCLK
36 M/S
35 AGND
34 OUTRP4
33 OUTRN4
32 OUTLP4
31 OUTLN4
30 AGND
29 AVDD
28 OUTRP3
27 OUTRN3
14 15 16 17 18 19 20 21 22 23 24 25 26
AD1835
Pin No.
1, 39
2
3
4
5, 10, 16, 24, 30, 35
6, 12, 25, 31
7, 13, 26, 32
8, 14, 27, 33
9, 15, 28, 34
11, 19, 29
17
18
20
21
22
23
36
37
38
40, 52
41–44
45
46
47
48
49
50
51
REV. PrA
Mnemonic
DVDD
CLATCH
CIN
PD/RST
AGND
OUTLNx
OUTLPx
OUTRNx
OUTRPx
AVDD
FILTD
FILTR
ADCLN
ADCLP
ADCRN
ADCRP
M/S
DLRCLK
DBCLK
DGND
DSDATAx
ABCLK
ALRCLK
MCLK
ODVDD
ASDATA
COUT
CCLK
PIN FUNCTION DESCRIPTIONS
Input/
Output Description
Digital Power Supply. Connect to digital 5 V supply.
I Latch Input for Control Data
I Serial Control Input
I Power-Down/Reset
Analog Ground
O DACx Left Channel Negative Output
O DACx Left Channel Positive Output
O DACx Right Channel Negative Output
O DACx Right Channel Positive Output
Analog Power Supply. Connect to analog 5 V supply.
Filter Capacitor Connection. Recommended 10 µF 100 nF.
Reference Filter Capacitor Connection. Recommended 10 µF 100 nF.
I ADC Left Channel Negative Input
I ADC Left Channel Positive Input
I ADC Right Channel Negative Input
I ADC Right Channel Positive Input
I ADC Master/Slave Select
I/O DAC LR Clock
I/O DAC Bit Clock
Digital Ground
I DACx Input Data (Left and Right Channels)
I/O ADC Bit Clock
I/O ADC LR Clock
I Master Clock Input
Digital Output Driver Power Supply
O ADC Serial Data Output
O Output for Control Data
I Control Clock Input for Control Data
–7–

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