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AD1836 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD1836은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AD1836 자료 제공

부품번호 AD1836 기능
기능 Multichannel 96 kHz Codec
제조업체 Analog Devices
로고 Analog Devices 로고


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AD1836 데이터시트, 핀배열, 회로
PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
Multichannel 96 kHz Codec
AD1836
FEATURES
5 V Multichannel Audio System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulators with Data Directed
Scrambling
Data-Directed Scrambling ADCs and DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –92 dB THD + N, 105 dB SNR and Dynamic Range
DACs: –95 dB THD + N, 108 dB SNR and Dynamic Range
On-Chip Volume Control with “Autoramp” Function
Programmable Gain Amplifier for ADC Input
Hardware and Software Controllable Clickless Mute
Digital De-Emphasis Processing
Supports 256 ؋ fS, 512 ؋ fS, or 768 ؋ fS Master Clock
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
52-Lead MQFP (PQFP) Plastic Package
APPLICATIONS
Home Theatre Systems
Automotive Audio Systems
DVD
Set-Top Boxes
Digital Audio Effects Processors
GENERAL DESCRIPTION
The AD1836 is a high-performance, single-chip codec pro-
viding three stereo DACs and two stereo ADCs using ADI’s
patented multibit sigma-delta architecture. An SPI port is
included, allowing a microcontroller to adjust volume and
many other parameters. The AD1836 operates from a 5 V
supply, with provision for a separate output supply to interface
with low-voltage external circuitry. The AD1836 is available
in a 52-lead MQFP (PQFP) package.
FUNCTIONAL BLOCK DIAGRAM
CCLK CDATA CLATCH COUT
MCLK
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
ALRCLK
ABCLK
ASDATA1
ASDATA2
AIN1L
AIN1R
CAPL1
AIN2L1
AIN2L2
CAPL2
CAPR1
AIN2R1
AIN2R2
CAPR2
SERIAL
DATA
I/O
PORT
CONTROL PORT
CLOCK
VOLUME
VOLUME
DIGITAL
FILTER
⌺⌬
DAC
⌺⌬
ADC1L
48/96kHz
⌺⌬
ADC1R
48/96kHz
DIGITAL
FILTER
48/96kHz
DIGITAL
FILTER
48/96kHz
PGA
⌺⌬
ADC2L
48kHz
DIGITAL
FILTER
48kHz
VOLUME
VOLUME
DIGITAL
FILTER
VOLUME
VOLUME
DIGITAL
FILTER
⌺⌬
DAC
⌺⌬
DAC
PGA
⌺⌬
ADC2R
48kHz
DIGITAL
FILTER
48kHz
2
PWRDWN/RESET AVDD
4
AGND
3
DVDD
VREF
2
DGND
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
FILTD
FILTR
SHARC is a registered trademark of Analog Device, Inc.
REV. PrC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001




AD1836 pdf, 반도체, 판매, 대치품
PRELIMINARY TECHNICAL DATA
AD1836–SPECIFICATIONS
TIMING (continued)
Parameter
ADC Serial Port
Normal Modes
tABH
ABCLK Delay High
Min Max Unit
max ns
tABL ABCLK Delay Low
max ns
tALS
tABDD
tALRDD
LRCLK Delay
ASDATA Delay
ASDATA Delay
Packed 128, 256 Modes
tABH ABCLK Delay High
max ns
max ns
max ns
max ns
tABL ABCLK Delay Low
max ns
tALS
tABDD
tALRDD
LRCLK Delay
ASDATA Delay
ASDATA Delay
TDM PACKED AUX, MASTER MODE
tABH ABCLK Delay High
max ns
max ns
max ns
max ns
tABL ABCLK Delay Low
max ns
tXBH AUXBCLK Delay High
max ns
tXBL AUXBCLK Delay Low
max ns
tALS
tXLS
tABDD
tALRDD
tDDS
tDDH
tDDS
tDDH
tDXDD
tDXDD
LRCLK Delay
AUXLRCLK Delay
ASDATA Delay
ASDATA Delay
AAUXDATA Setup
AAUXDATA Hold
DSDATA Setup
DSDATA Hold
DAUXDATA Delay
DAUXDATA Delay
max ns
max ns
max ns
max ns
min ns
min ns
min ns
min ns
max ns
max ns
Comments
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256× fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From MCLK Rising
256 × fS
512 × fS
768 × fS
From ABCLK Falling
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
To AUXBCLK Rising
From AUXBCLK Rising
To DBCLK Rising
From DBCLK Rising
From AUXBCLK Falling
From AUXLRCLK Changing
(Left-Justified)
–4– REV. PrC

4페이지










AD1836 전자부품, 판매, 대치품
PRELIMINARY TECHNICAL DATA
PIN
No.
1, 40
2
3
4
5
6
7
8
9
10, 15
11, 14, 28, 29
12
13
16
17
18
19
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
38
39, 52
41
42
43
44
45
46
47
48
49
50
51
52
Mnemonic
DVDD
CDATA
PD/RST
OUTLP3
OUTLN3
OUTLP2
OUTLN2
OUTLP1
OUTLN1
AVDD
AGND
FILTD
FILTR
ADC1INLP
ADC1INLN
ADC1INRP
ADC1INRN
ADC2INL+/CAPL2
ADC2INL–/CAPL1
ADC2INL1
ADC2INL2
ADC2INR2
ADC2INR1
ADC2INR–/CAPR1
ADC2INR+/CAPR2
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
OUTRP3
DLRCLK
DBCLK
DSDATA1
DGND
DSDATA2
DSDATA3
ABCLK
ALRCLK
MCLK
ODVDD
ASDATA1
ASDATA2
COUT
CLATCH
CCLK
DGND
PIN FUNCTION DESCRIPTIONS
AD1836
In/Out
I
I
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
I/O
I/O
I
I
I
I
O
O
I
I
O
O
O
I
I
I
Description
Digital Power Supply. Connect to digital 5 V supply.
Serial Control Input
Power-Down Reset
DAC 3 (Left) Positive Output
DAC 3 (Left) Negative Output
DAC 2 (Left) Positive Output
DAC 2 (Left) Negative Output
DAC 1 (Left) Positive Output
DAC 1 (Left) Negative Output
Analog Power Supply. Connect to analog 5 V.
Analog Ground
Filter Capacitor Connection. Recommend 10 µF//100 nF.
Voltage Reference Filter Capacitor Connection. Recommend 10 µF//100 nF.
ADC1 Left Positive Input
ADC1 Left Negative Input
ADC1 Right Positive Input
ADC1 Right Negative Input
ADC2 Left Positive Input (Direct Mode)/ADC2 Left Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Left Negative Input (Direct Mode)/ADC2 Left Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Left Input 2 (MUX/PGA Mode)/Left Positive Input (PGA Differ-
ential Mode)
ADC2 Left Input 1 (MUX/PGA Mode)/Left Negative Input (PGA Differ-
ential Mode)
ADC2 Right Input 1 (MUX/PGA Mode)/Right Negative Input (PGA
Differential Mode)
ADC2 Right Input 2 (MUX/PGA Mode)/Right Positive Input (PGA
Differential Mode)
ADC2 Right Negative Input (Direct Mode)/ADC2 Right Decoupling Cap
(MUX/PGA and PGA Differential Mode)
ADC2 Right Positive Input (Direct Mode)/ADC2 Right Decoupling Cap
(MUX/PGA and PGA Differential Mode)
DAC 1 (Right) Negative Output
DAC 1 (Right) Positive Output
DAC 2 (Right) Negative Output
DAC 2 (Right) Positive Output
DAC 3 (Right) Negative Output
DAC 3 (Right) Positive Output
LR Clock for DACs
Bit Clock for DACs
DAC Input #1 (Input to DAC1 and DAC2)
Digital Ground
DAC Input #2 (Input to DAC3 and DAC4)
DAC Input #3 (Input to DAC5 and DAC6)
Bit Clock for ADCs
LR Clock for ADCs
Master Clock Input
Digital Output Driver Power Supply
ADC Serial Data Output #1
ADC Serial Data Output #2
Output for Control Data
Latch Input for Control Data
Control Clock Input for Control Data
Digital Ground
REV. PrC
–7–

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