|
|
PDF AD1838A Data sheet ( Hoja de datos )
| Número de pieza | AD1838A | |
| Descripción | 2 ADC/ 6 DAC/ 96KHZ 24 BIT CODEC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD1838A (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
|
No Preview Available !
a
2 ADC, 6 DAC,
96 kHz, 24-Bit ⌺-⌬ Codec
AD1838A
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant
Digital Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on 1 DAC
Supports 16-, 20-, 24-Bit Word Lengths
Multibit ⌺-⌬ Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –95 dB THD + N, 108 dB SNR and
Dynamic Range
On-Chip Volume Controls per Channel with
1024 Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
Supports 256 ؋ fS, 512 ؋ fS, and 768 ؋ fS Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
GENERAL DESCRIPTION
The AD1838A is a high performance single-chip codec featuring
three stereo DACs and one stereo ADC. Each DAC comprises a
high performance digital interpolation filter, a multibit ⌺-⌬
modulator featuring Analog Devices’ patented technology,
and a continuous-time voltage out analog section. Each DAC
has independent volume control and clickless mute functions.
The ADC comprises two 24-bit conversion channels with
multibit ⌺-⌬ modulators and decimation filters.
The AD1838A also contains an on-chip reference with a nomi-
nal value of 2.25 V.
The AD1838A contains a flexible serial interface that allows
glueless connection to a variety of DSP chips, AES/EBU
receivers, and sample rate converters. The AD1838A can be
configured in left-justified, right-justified, I2S, or DSP com-
patible serial modes. Control of the AD1838A is achieved by
means of an SPI® compatible serial port. While the AD1838A
can be operated from a single 5 V supply, it also features a sepa-
rate supply pin for its digital interface that allows the device to
be interfaced to other devices using 3.3 V power supplies.
The AD1838A is available in a 52-lead MQFP package and is
specified for the industrial temperature range of –40ºC to +85ºC.
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT MCLK PD/RST M/S AVDD AVDD
AAUXDATA3
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DAUXDATA
ADCLP
ADCLN
ADCRP
ADCRN
⌺−∆
ADC
⌺−∆
ADC
SERIAL DATA
I/O PORT
DIGITAL
FILTER
DIGITAL
FILTER
CONTROL PORT
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
CLOCK
DIGITAL
FILTER
DIGITAL
FILTER
DIGITAL
FILTER
AD1838A
⌺-⌬
DAC
⌺-⌬
DAC
⌺-⌬
DAC
VREF
OUTLP1
OUTLN1
OUTRP1
OUTRN1
OUTLP2
OUTLN2
OUTRP2
OUTRN2
OUTLP3
OUTLN3
OUTRP3
OUTRN3
FILTD
FILTR
REV. A
DGND DGND AGND AGND AGND AGND
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
TDM256 MODE (Master, 48 kHz and 96 kHz)
tTBD
tFSD
tTABDD
tTDDS
tTDDH
BCLK Delay
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB
tTBCH
BCLK Frequency
BCLK High
tTBCL
tTFS
tTFH
BCLK Low
FSTDM Setup
FSTDM Hold
tTBDD
tTDDS
tTDDH
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
TDM512 MODE (Master, 48 kHz)
tTBD
tFSD
tTABDD
tTDDS
tTDDH
BCLK Delay
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
TDM512 MODE (Slave, 48 kHz )
fAB
tTBCH
BCLK Frequency
BCLK High
tTBCL
tTFS
tTFH
BCLK Low
FSTDM Setup
FSTDM Hold
tTBDD
tTDDS
tTDDH
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
AUXILIARY INTERFACE (48 kHz and 96 kHz)
tAXDS
tAXDH
tDXD
fABP
Slave Mode
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK Frequency
tAXBH
tAXBL
tAXLS
tAXLH
Master Mode
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
tAUXBCLK
tAUXLRCLK
AUXBCLK Delay
AUXLRCLK Delay
Specifications subject to change without notice.
Min
15
15
256 ϫ fS
17
17
10
10
15
15
15
15
512 ϫ fS
17
17
10
10
15
15
10
10
20
64 ϫ fS
15
15
10
10
20
15
Max
40
5
10
15
40
5
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK
PD/RST
tMCLK
tMH
tML
tPDR
Figure 1. MCLK and PD/RST Timing
REV. A
–5–
AD1838A
Comments
From MCLK Rising Edge
From BCLK Rising Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
To BCLK Falling Edge
From BCLK Falling Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
From MCLK Rising Edge
From BCLK Rising Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
To BCLK Falling Edge
From BCLK Falling Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
To AUXBCLK Rising Edge
From AUXBCLK Rising Edge
From AUXBCLK Falling Edge
To AUXBCLK Rising Edge
From AUXBCLK Rising Edge
From MCLK Rising Edge
From AUXBCLK Falling Edge
5 Page 
AD1838A
FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1838A, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an oversam-
pling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz
operation).
ADC peak level information for each ADC may be read from the
ADC Peak 0 and ADC Peak 1 registers. The data is supplied
as a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information
until read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description for
details of the format. The two ADC channels have a common
serial bit clock and a left-right framing clock. The clock signals
are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1838A will generate the timing signals.
When the pins are set as inputs, the timing must be generated
by the external audio controller.
Table I. Coding Scheme
Code
Level
0111 . . . . 11111
0000 . . . . 00000
1000 . . . . 00000
+FS
0 (Ref Level)
–FS
AD1838A CLOCKING SCHEME
By default, the AD1838A requires an MCLK signal that is
256 times the required sample frequency up to a maximum of
12.288 MHz. The AD1838A uses a clock scaler to double the
clock frequency for use internally. The default setting of the
clock scaler is Multiply by 2. The clock scaler can also be set
Multiply by 1 (bypass) or by 2/3. The clock scaler is controlled
by programming the bits in the ADC Control 3 register. The
internal MCLK signal, IMCLK, should not exceed 24.576 MHz
to ensure correct operation.
The MCLK of the AD1838A should remain constant during
normal operation of the DAC and ADC. If it is required to change
the MCLK rate, then the AD1838A should be reset. Additionally,
if MCLK scaler needs to be modified so that the IMCLK does not
exceed 24.576 MHz, this should be done during the internal reset
phase of the AD1838A by programming the bits in the first
3072 MCLK periods following the reset.
DACs
The AD1838A has six DAC channels arranged as three inde-
pendent stereo pairs, with six fully differential analog outputs
for improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through three
serial data input pins (one for each stereo pair) and a common
frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one of
the packed data modes may be used to access all six channels on a
single TDM data pin. A stereo replicate feature is included where
the DAC data sent to the first DAC pair is also sent to the
other DACs in the part. The AD1838A can accept DAC data at
a sample rate of 192 kHz on DAC 1 only. The stereo repli-
cate feature can then be used to copy the audio data to the
other DACs.
Each set of differential output pins sits at a dc level of VREF and
swings ± 1.4 V for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. Note that the use
of op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect on
performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos complement
encoded format. The word width can be selected from 16 bit,
20 bit, or 24 bit. The coding scheme is detailed in Table I.
Selecting DAC Sampling Rate
The AD1838A DAC engine has a programmable interpolator
that allows the user to select different interpolation rates based
on the required sample rate and MCLK value available. Table II
shows the settings required for sample rates based on a fixed
MCLK of 12.288 MHz.
Table II. DAC Sample Rate Settings
Sample Rate
48 kHz
96 kHz
192 kHz
Interpolator Rate DAC Control 1 Register
8ϫ 000000xxxxxxxx00
4ϫ 000000xxxxxxxx01
2ϫ 000000xxxxxxxx10
Selecting an ADC Sample Rate
The AD1838A ADC engine has a programmable decimator that
allows the user to select the sample rate based on the MCLK
value. By default, the output sample rate is IMCLK/512. To
achieve a sample rate of IMCLK/256, the sample rate bit in the
ADC Control 1 register should be set as shown in Table III.
Table III. ADC Sample Rate Settings
Sample Rate
IMCLK/512
IMCLK/256
ADC Control 1 Register
1100000xx0xxxxxx (48 kHz)
1100000xx1xxxxxx (96 kHz)
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less than
300 ps rms, measured using the edge-to-edge technique. Even at
these levels, extra noise or tones may appear in the DAC outputs if
the jitter spectrum contains large spectral peaks. It is highly recom-
mended that the master clock be generated by an independent
crystal oscillator. In addition, it is especially important that the
clock signal should not be passed through an FPGA or other large
digital chip before being applied to the AD1838A. In most cases,
this will induce clock jitter because the clock signal is sharing
common power and ground connections with other unrelated
digital output signals.
REV. A
–11–
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD1838A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD1838A | 2 ADC/ 6 DAC/ 96KHZ 24 BIT CODEC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |