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PDF AD1843 Data sheet ( Hoja de datos )
| Número de pieza | AD1843 | |
| Descripción | Serial-Port 16-Bit SoundComm Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Serial-Port 16-Bit
SoundComm Codec
AD1843
FEATURES
Single Chip Integrated Speech, Audio, Fax and Modem
Codec
Highly Configurable Stereo ∑∆ ADCs and Quad ∑∆ DACs
Supports V.34, V.32bis, and Fallback Modem Standards
As Well As Voice Over Data
Dual Digital Resamplers with Programmable Input and
Output Phase and Frequency
Three On-Chip Phase Lock Loops for Synchronization to
External Signals, Including Video
Thirteen Analog Inputs and Seven Analog Outputs
Advanced Analog and Digital Signal Mixing and Digital-
to-Digital Sample Rate Conversion
Programmable Gain, Attenuation and Mute
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low Pass
1 Hz Resolution Programmable Sample Rates from 4 kHz
to 54 kHz Derived from a Single Clock Input
80-Lead PQFP and 100-Lead TQFP Packages
Operation from +5 V or Mixed +5 V/+3 V Supplies
FIFO-Buffered Serial Digital Interface Compatible with
ADSP-21xx Fixed-Point DSPs
Advanced Power Management
VHDL Model of Serial Port Available; Evaluation Board
and MAFE Board Available
GENERAL PRODUCT DESCRIPTION
The AD1843 SoundComm™ Codec is a complete analog front
end for high performance DSP-based telephony and audio ap-
plications. The device integrates the real-world analog I/O re-
quirements for many popular functions thereby reducing size,
power consumption, and system complexity. The AD1843
SoundComm is the world’s first codec which can support four
different sample rates simultaneously, without any beat fre-
quency noise issues. This is essential for highly integrated audio/
modem/fax products since the sample rates associated with au-
dio are very much distinct from the sample rates associated with
telephony-oriented data communication. It is also the first codec
to offer on-chip digital phase lock loops for sample rate synchro-
nization to external clock signals. This sample rate flexibility is
enabled through Analog Devices’ Continuous Time Oversampling
(CTO) technology.
The main elements of the AD1843 are its extensive input and mix-
ing section, its two channels of sigma-delta (∑∆) analog-to-digital
conversion, its four channels of ∑∆ digital-to-analog conversion, its
digital filters, and the clock and control circuitry for implementing
the device’s different modes. The AD1843 permits flexible sample-
rate selection through programming and external synchronization,
many input and output options, and many mixing options.
(continued on page 11)
SoundComm is a trademark of Analog Devices, Inc.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
SYNC XTAL CONV BIT
LIN 4
MIC
AUX1
AUX2
AUX3
MIN
2
2
2
2
1
MOUT
2
LOUT1
HPOUTL
HPOUTC
HPOUTR
LOUT2
SUM
4
2
3233
20 dB
AD1843
S
CLOCK GENERATION
CLKOUT
E CONTROL
MUTE
MUTE
L
E
C
T
O
R
GAM GAM GAM GAM GAM
PGA
∑∆
ADC
S
E
L
E
C
T
O
R
S
E
L
E
C
T
O
R
ATTN
MUTE
∑
∑
∑
∑
∑
GAM
∑∆
DAC
LEFT AND
M
∑
U
T
ATTN ∑
E
REGISTERS
µ/A
LAW
FIFO
µ/A
LAW
ADC
D
I
G
I
T
A
L
DAC1
I
SCLK
SDFS
SDI
SDO
BM
CS
TSO
DRIVER
RIGHT CHANNELS
MUTE
GAM
MUTE
ATTN
N
T TSI
E2
MUTE
GAM = GAIN
ATTENUATION
MUTE
MUTE
MUTE
R XCTL [1:0]
F
A PDMNFT
C
LEFT AND
RIGHT CHANNELS
GAM
VOLTAGE REFERENCE
∑∆
DAC
M
∑
U
T
ATTN
E
E
∑
FIFO
µ/A
LAW
DAC2
RESET
PWRDWN
43
89
REV. 0
VREF CMOUT
AAFILTL AAFILTR
FILTL FILTR
GNDA VCC
GNDD VDD
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD1843
ANALOG OUTPUT
LOUT1 Full-Scale Output Voltage
(RMS Values Assume Sine Wave Input)
LOUT2 Full-Scale Single-Ended Output Voltage
(RMS Values Assume Sine Wave Input)
LOUT2 Full-Scale Differential Output Voltage
(RMS Values Assume Sine Wave Input)
LOUT1 Output Impedance*
LOUT2 Output Impedance*
LOUT1 External Load Impedance*
LOUT2 External Load Impedance*
MOUT External Load Impedance*
HPOUT External Load Impedance*
HPOUT THD+N (Referenced to Full Scale, 32 Ω External Load Impedance)
Output Capacitance*
External Load Capacitance*
CMOUT
External CMOUT Load Current*
CMOUT Output Impedance*
Mute Click* (Muted Output Minus Unmuted Midscale DAC1 and DAC2 Outputs)
Min
1.8
1.8
3.6
10
2
10
16
2.10
Typ
0.707
2.0
0.707
2.0
1.414
4.0
Max
2.2
2.2
4.4
600
1
32
0.10
–60
15
100
2.25 2.40
10
4
±5
Units
V rms
V p-p
V rms
V p-p
V rms
V p-p
Ω
Ω
kΩ
kΩ
kΩ
Ω
%
dB
pF
pF
V
µA
kΩ
mV
SYSTEM SPECIFICATIONS
System Frequency Response Ripple* (Line-In to Line-Out)
Differential Nonlinearity*
Phase Linearity Deviation*
Max Units
1.0 dB
±1 Bit
5 Degrees
STATIC DIGITAL SPECIFICATIONS
High-Level Input Voltage (VIH)
Digital Inputs, Except SCLK
XTALI and SCLK
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH)
Low-Level Output Voltage (VOL)
Input Leakage Current (GO/NOGO Tested)
Output Leakage Current (GO/NOGO Tested)
Min Max Units
2.0 VDD+ 0.3 V
2.4 VDD+ 0.3 V
–0.3 0.8
V
2.4 V
0.4 V
–10 10
µA
–10 10
µA
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE AND DIGITAL SUPPLY RANGE)
Min Typ Max Units
Serial Data Frame Sync [SDFS] Period (t1)
(Master Mode, FRS = 1 [16 Slots per Frame], SCF = 0 [SCLK = 12.288 MHz])
Frame Sync [SDFS] HI Pulse Width (t2)
Clock [SCLK] to Frame Sync [SDFS] Propagation Delay (tPD1)
Data [SDI] Input Setup Time to SCLK (tS)
Data [SDI] Input Hold Time from SCLK (tH)
Clock [SCLK] to Output Data [SDO] Valid (tDV)
Clock [SCLK] to Output Data [SDO] Three-State [High-Z] (tHZ)
Clock [SCLK] to Time Slot Output [TSO] Propagation Delay (tPD2)
RESET and PWRDWN LO Pulse Width (tRPWL)
10
10
100
20.833
80
15
15
15
15
µs
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
SDFS
SDI
SDO
t2
tPD1
tS tH
BIT 15
BIT 15
BIT 14
tDV
BIT 14
REV. 0
BIT 0
tHZ
BIT 0
SCLK
SDFS
SDI OR SDO
TSO
tPD1
15 14 13
RESET
PWRDWN
Figure 1. Timing Diagrams
–5–
tRPWL
t1
3 2 1 0 15 14 13
LAST
VALID
TIME SLOT
tPD2
15 1413
5 Page 
POWER SUPPLIES
Pin Name PQFP
TQFP
I/O Description
VCC
GNDA
VDD
GNDD
NC
20, 41, 44 25, 51, 55 I
21, 37, 40, 48 27, 46, 49, 59 O
4, 8, 50, 53, 5, 10, 62, 66, I
63, 64, 68, 72, 79, 80, 85, 90,
77 96
3, 7, 54, 60, 4, 9, 67, 75, I
65, 69, 73, 78 81, 86, 91, 97
3, 8, 13, 14,
24, 26, 32, 37,
42, 50, 52, 60,
63, 68, 73, 78,
83, 88, 93, 98
Analog Supply Voltage (+5 V).
Analog Ground.
Digital Supply Voltage (+5/3 V).
Digital Ground.
No Connect. May be left floating.
AD1843
(continued from page 1)
The versatility of the device is shown by the following examples
of functions it can perform:
• Stereo audio input and/or quad output, simultaneously at dif-
ferent sample rates
• Stereo audio output with simultaneous full duplex modem or
fax operation with frequency and phase resampling
• Mono audio input and stereo audio output with simultaneous
modem receive and transmit for simultaneous voice and data
communications
• Dual independent audio inputs with audio output for echo-
cancelling speakerphones
Audio Functional Description
The AD1843 SoundComm codec provides a complete audio so-
lution with very few external components required. Dynamic
range of the device exceeds 80 dB over the 20 kHz audio band
and sample rates from 4 kHz to 49 kHz are supported (up to
54 kHz for a single channel if other channels are powered
down). The audio functionality of this device is a superset of
that found in the Analog Devices AD1848 SoundPort® device
which has set the business audio standard throughout the com-
puter industry.
Inputs to the device include a stereo microphone pair, a stereo
line pair, a stereo CD input pair (AUX1), a stereo synthesized
music input pair (AUX2), a dual phone line input (AUX3), a
mono input, and a stereo input from an FM synthesizer (SUM).
All of these inputs (except SUM) are multiplexed to the two ∑∆
A/D converters and are mixable directly as analog signals with
the outputs of the D/A converters. All analog input signals (ex-
cept SUM) can be amplified, attenuated or muted before mix-
ing with the outputs of the D/A converters.
The device has two pairs of ∑∆ DACs which accept 8- or 16-bit
digital data from the serial port. Each DAC pair’s independent
sampling rate can either be programmed by Control Register
(with 1 Hz resolution) or synchronized to an external input.
The second pair of DACs can be used to replace the music syn-
thesis DAC pair found on many audio products for PCs. Out-
puts from the AD1843 include a line output, a mono output, a
stereo headphone output with its own current return path, and a
SoundPort is a registered trademark of Analog Devices, Inc.
differential stereo output for connection to a DAA. The line and
differential outputs are looped back to the ADC input selector.
The AD1843’s mixing and routing capabilities are extensive.
The digital data from both DAC channels after interpolation
can be routed back to the ADC decimators, to support digital-
to-digital sample rate conversion (digital resampling). Digital
data from the ADC can also be routed to the two stereo DAC
pairs, for a digital loopback mode which is helpful for device-
level and board-level test. Digital data from either stereo DAC
can be mixed with the digital data feeding the other DAC, and
the analog signal from DAC2 can be mixed with the analog out-
put from DAC1.
Sample rates are independently programmable in the range of
4 kHz to 54 kHz to a 1 Hz resolution or sample rates can be
synchronized to an external source. Up to three different signals
can be applied to the device’s three digital phase lock loop
SYNC inputs for external synchronization.
These SYNC inputs can also be used in a special mode for au-
dio/video synchronization. In this mode, an NTSC or PAL de-
rived clock signal (approximately 15 kHz) is applied to the
SYNC inputs and the device produces one of a variety of stan-
dard audio sample rates (32 kHz, 44.056 kHz, 44.1 kHz and
48 kHz, and most of these divided by the integers 1 through 8).
In this manner, video and audio sample rates which are math-
ematically unrelated can be locked together.
Data Communications/Telephony Functional Description
The AD1843 includes all data conversion, filtering, and clock
generation circuitry needed to implement an echo-cancelling
modem with a companion digital signal processor. Software-
programmable sample rates and clocking modes support all
established modem standards including those for the V.34
standard.
The AD1843 utilizes advanced ∑∆ technology to move the
entire echo-cancelling modem implementation into the digital
domain. The device maintains 90 dB typical dynamic range
throughout all filtering and data conversion across a 9.6 kHz
passband. Purely DSP-based echo cancellation algorithms can
maintain robust bit error rates under worst-case signal attenua-
tion and echo amplitude conditions. The AD1843’s on-chip
interpolation filter resamples (both frequency and phase) the re-
ceived signal after echo cancellation in the DSP, freeing the pro-
cessor for other voice or data communications tasks.
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD1843.PDF ] | |
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