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부품번호 | AD1845 기능 |
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기능 | Parallel-Port 16-Bit SoundPort Stereo Codec | ||
제조업체 | Analog Devices | ||
로고 | |||
전체 30 페이지수
a
Parallel-Port 16-Bit
SoundPort® Stereo Codec
AD1845
FEATURES
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Microsoft® and Windows® Sound System Compatible
MPC Level-2+ Compliant Mixing
16 mA Bus Drive Capability
Supports Two DMA Channels for Full Duplex Operation
On-Chip Capture and Playback FIFOs
Advanced Power-Down Modes
Programmable Gain and Attenuation
Sample Rates from 4.0 kHz to 50 kHz Derived from a
Single Clock or Crystal Input
68-Lead PLCC, 100-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Pin Compatible with AD1848, AD1846, CS4248, CS4231
PRODUCT OVERVIEW
The Parallel Port AD1845 SoundPort Stereo Codec integrates
key audio data conversion and control functions into a single
integrated circuit. The AD1845 provides a complete, single chip
computer audio solution for business audio and multimedia
applications. The codec includes stereo audio converters, com-
plete on-chip filtering, MPC Level-2 compliant analog mixing,
programmable gain, attenuation and mute, a variable sample
frequency generator, FIFOs, and supports advanced power-
down modes. It provides a direct, byte-wide interface to both
ISA (“AT”) and EISA computer buses for simplified implemen-
tation on a computer motherboard or add-in card.
The AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
Two input control lines support mixed direct and indirect ad-
dressing of thirty-seven internal control registers over this asyn-
chronous interface. The AD1845 includes dual DMA count
registers for full duplex operation enabling the AD1845 to cap-
ture data on one DMA channel and play back data on a separate
channel. The FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. The
FIFOs buffer data transfers and allow for relaxed timing in
acknowledging requests for capture and playback data.
(Continued on Page 9)
FUNCTIONAL BLOCK DIAGRAM
ANALOG
ANALOG SUPPLY
DIGITAL SUPPLY
CLOCK SOURCE POWER DOWN
RESET
DIGITAL
L_MIC
R_MIC
L_LINE
R_LINE
L_AUX1
R_AUX1
L_OUT
M_OUT
R_OUT
M_IN
L_AUX2
R_AUX2
0 dB/
20 dB
VARIABLE SAMPLE
FREQUENCY GENERATOR
L
M
U
XR
GAIN
GAIN
⌺⌬ A/D
CONVERTER
⌺⌬ A/D
CONVERTER
AD1845
-LAW
A-LAW
LINEAR
FIFO
MUTE
GAM
⌺
⌺
⌺
GAM
⌺
⌺
GAM
⌺
GAM = GAIN
ATTENTUATE
MUTE
DIGITAL MIX
ATTENUATE
L ATTENUATE
MUTE
⌺⌬ D/A
CONVERTER
⌺
R
⌺
ATTENUATE
MUTE
⌺⌬ D/A
CONVERTER
⌺
-LAW
A-LAW
LINEAR
GAM
GAM
FIFO
P
A
R
A
L
L
E
L
P
O
R
T
PLAYBACK REQ
PLAYBACK ACK
CAPTURE REQ
CAPTURE ACK
ADR1:0
DATA7:0
CS
RD
WR
BUS DRIVER
CONTROL
HOST DMA
INTERRUPT
EXTERNAL
CONTROL
REFERENCE
CONTROL
REGISTERS
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
VREF_F VREF
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
AD1845
SYSTEM SPECIFICATIONS
System Frequency Response Ripple (Line In to Line Out)*
Differential Nonlinearity*
Phase Linearity Deviation*
Min Typ Max
1.0
±1
5
STATIC DIGITAL SPECIFICATIONS
High Level Input Voltage (VIH)
Digital Inputs
XTAL1I
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH) IOH = –2 mA
Low Level Output Voltage (VOL) IOL = 2 mA
Input Leakage Current
Output Leakage Current
Min Max
2.4
2.4
0.8
2.4
0.4
–10 10
–10 10
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE, VDD = VCC = 5.0 V)
Min Max
WR/RD Strobe Width
WR/RD Rising to WR/RD Falling
Write Data Setup to WR Rising
RD Falling to Valid Read Data
CS Setup to WR/RD Falling
CS Hold from WR/RD Rising
Adr Setup to WR/RD Falling
Adr Hold from WR/RD Rising
DAK Rising to WR/RD Falling
DAK Falling to WR/RD Rising
DAK Setup to WR/RD Falling
Data Hold from RD Rising
Data Hold from WR Rising
DRQ Hold from WR/RD Falling
DAK Hold from WR Rising
DAK Hold from RD Rising
DBEN/DBDIR Delay from WR/RD Falling
PWRDWN and RESET Low Pulsewidth
(tSTW)
(tBWND)
(tWDSU)
(tRDDV)
(tCSSU)
(tCSHD)
(tADSU)
(tADHD)
(tSUDK1)
(tSUDK2)
(tDKSU)
(tDHD1)
(tDHD2)
(tDRHD)
(tDKHDa)
(tDKHDb)
(tDBDL)
100
80
10
40
10
0
10
10
20
0
10
20
15
25
10
10
30
300
*Guaranteed, not tested.
Units
dB
LSB
Degrees
Units
V
V
V
V
V
µA
µA
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–4– REV. C
4페이지 AD1845
Parallel Interface
Pin Name PLCC TQFP
CDRQ
12 7
I/O
O
CDAK
PDRQ
11 6
14 9
I
O
PDAK
ADR1:0
13 8
I
9 & 10 100 & 1 I
RD
60 75
I
WR
61 76
I
CS
59 74
I
DATA7:0
DBEN
3–6 & 84–87 & I/O
65–68 90–93
63 78
O
DBDIR
62 77
O
PIN FUNCTION DESCRIPTIONS
Description
Capture Data Request. The assertion of this signal HI indicates that the codec has a cap-
tured audio sample from the ADC ready for transfer. This signal will remain asserted
until the internal capture FIFO is empty.
Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD
cycle occurring is a DMA read from the capture buffer.
Playback Data Request. The assertion of this signal HI indicates that the codec is ready
for more DAC playback data. The signal will remain asserted until the internal playback
FIFO is full.
Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR
cycle occurring is a DMA write to the playback buffer.
Codec Addresses. These address pins are asserted by the codec interface logic during a
control register/PIO access. The state of these address lines determine which direct
register is accessed.
Read Command Strobe. This active LO signal defines a read cycle from the codec. The
cycle may be a read from the control/PIO registers, or the cycles could be a read from
the codec’s DMA sample registers.
Write Command Strobe. This active LO signal indicates a write cycle to the codec. The
cycle may be a write to the control/PIO registers, or the cycle could be a write to the
codec’s DMA sample registers.
AD1845 Chip Select. The codec will not respond to any control/PIO cycle accesses
unless this active LO signal is LO. This signal is ignored during DMA transfers.
Data Bus. These pins transfer data and control information between the codec and
the host.
Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.
For control register/PIO cycles,
DBEN = (WR or RD) and CS
For DMA cycles,
DBEN = (WR or RD) and (PDAK or CDAK).
Data Bus Direction. This pin controls the direction of the data bus transceiver. HI
enables writes from the host bus to the AD1845; LO enables reads from the AD1845 to
the host bus. This signal is normally HI.
For control register/PIO cycles,
DBDIR = RD and CS
For DMA cycles,
DBDIR = RD and (PDAK or CDAK).
REV. C
–7–
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
AD1843 | Serial-Port 16-Bit SoundComm Codec | Analog Devices |
AD1845 | Parallel-Port 16-Bit SoundPort Stereo Codec | Analog Devices |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |