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부품번호 AD1847 기능
기능 Serial-Port 16-Bit SoundPort Stereo Codec
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AD1847 데이터시트, 핀배열, 회로
a
Serial-Port 16-Bit
SoundPort Stereo Codec
AD1847
FEATURES
Single-Chip Integrated ⌺⌬ Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V Supplies
Serial Digital Interface Compatible with ADSP-21xx
Fixed-Point DSP
PRODUCT OVERVIEW
The AD1847 SoundPort® Stereo Codec integrates key audio
data conversion and control functions into a single integrated
circuit. The AD1847 is intended to provide a complete, low
cost, single-chip solution for business, game audio and multi-
media applications requiring operation from a single +5 V sup-
ply. It provides a serial interface for implementation on a
computer motherboard, add-in or PCMCIA card. See Figure 1
for an example system diagram.
*Windows Sound System is a registered trademark of Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
I
S
A
ASIC
B
U
S DSP
AD1847
Figure 1. Example System Diagram
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 70 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.
The Codec includes a stereo pair of ∑∆ analog-to-digital con-
verters (ADCs) and a stereo pair of ∑∆ digital-to-analog con-
verters (DACs). Inputs to the ADC can be selected from four
stereo pairs of analog signals: line 1, line 2, auxiliary (“aux”)
line #1, and post-mixed DAC output. A software-controlled
programmable gain stage allows independent gain for each
channel going into the ADC. The ADCs’ output can be digitally
mixed with the DACs’ input.
The pair of 16-bit outputs from the ADCs is available over a se-
rial interface that also supports 16-bit digital input to the DACs
and control/status information. The AD1847 can accept and
generate 16-bit twos-complement PCM linear digital data, 8-bit
unsigned magnitude PCM linear data, and 8-bit µ-law or A-law
companded digital data.
(Continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
ANALOG ANALOG DIGITAL
I/O SUPPLY SUPPLY
LINE 1 L
INPUT R
LINE 2 L
INPUT R
AUX 1 L
INPUT R
ML
U
X
R
CLOCK
OUT
CRYSTALS
22
GAIN
GAIN
∑∆ A/D
CONVERTER
∑∆ A/D
CONVERTER
OSCILLATORS
µ/A
LAW
µ/A
LAW
L
LINE
OUTPUT
R
L
AUX 2
INPUT
R
GAIN/ATTEN/MUTE
ATTEN
L
ATTEN/
∑∆ D/A
MUTE CONVERTER
ATTEN
µ/A
LAW
R
ATTEN/
∑∆ D/A
MUTE CONVERTER
ATTEN
µ/A
LAW
GAIN/ATTEN
/MUTE
GAIN/ATTEN
/MUTE
REFERENCE
AD1847
S
E
R
I
A
L
P
O
R2
T
DIGITAL
I/O
RESET
POWER
DOWN
BUS
MASTER
TIME SLOT
INPUT
TIME SLOT
OUTPUT
SERIAL DATA
OUTPUT
SERIAL DATA
INPUT
EXTERNAL
CONTROL
SERIAL BIT
CLOCK
FRAME
SYNC
REV. B
2.25V
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
® Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD1847 pdf, 반도체, 판매, 대치품
AD1847
SYSTEM SPECIFICATIONS
System Frequency Response†
(Line In to Line Out, 20 Hz to 20 kHz)
Differential Nonlinearity†
Phase Linearity Deviation†
Min
Typ
± 0.3
1
STATIC DIGITAL SPECIFICATIONS
High Level Input Voltage (VIH)
Digital Inputs
XTAL1/2I
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH) IOH = 1 mA
Low Level Output Voltage (VOL) IOL = 4 mA
Input Leakage Current (GO/NOGO Tested)
Output Leakage Current (GO/NOGO Tested)
Min
2.0
2.4
2.4
–10
–10
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)
Min
Serial Frame Sync Period (t1)
Clock to Frame Sync [SDFS] Propagation Delay (tPD1)
Data Input Setup Time (tS)
Data Input Hold Time (tH)
Clock to Output Data Valid (tDV)
Clock to Output Three-State [High-Z] (tHZ)
Clock to Time Slot Output [TSO] Propagation Delay (tPD2)
RESET and PWRDOWN Lo Pulse Width (tRPWL)
POWER SUPPLY
15
15
100
Min
Power Supply Range – Digital & Analog
Power Supply Current – Operating (10 kLine Out Load)
Analog Supply Current – Operating (10 kLine Out Load)
Digital Supply Current – Operating (10 kLine Out Load)
Analog Power Supply Current – Power Down
Digital Power Supply Current – Power Down
Power Dissipation – Operating (Current ϫ Nominal Supply)
Power Dissipation – Power Down (Current ϫ Nominal Supply)
Power Supply Rejection (@ 1 kHz)†
(At Both Analog and Digital Supply Pins, ADCs)
(At Both Analog and Digital Supply Pins, DACs)
4.75
45
55
CLOCK SPECIFICATIONS†
Input Clock Frequency
Recommended Clock Duty Cycle
Initialization/Sample Rate Change Time
16.9344 MHz Crystal Selected at Power-Up
24.576 MHz Crystal Selected at Power-Up
16.9344 MHz Crystal Selected Subsequently
24.576 MHz Crystal Selected Subsequently
†Guaranteed, not tested.
Specifications subject to change without notice.
Min
–4–
Max
± 1/2
Max
0.8
VDD
0.4
+10
+10
Typ
1/0.5 FS
Max
20
25
20
20
Max
5.25
140
70
70
400
400
750
4
Max
27
± 10
171
171
6
6
Units
dB
Bit
Degrees
Units
V
V
V
V
V
µA
µA
Units
µs
ns
ns
ns
ns
ns
ns
ns
Units
V
mA
mA
mA
µA
µA
mW
mW
dB
dB
Units
MHz
%
ms
ms
ms
ms
REV. B

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AD1847 전자부품, 판매, 대치품
AD1847
Miscellaneous
Pin Name PLCC TQFP I/O
XTAL1I
XTAL1O
XTAL2I
XTAL2O
XCTL1:O
40
41
42
43
37 & 36
34
35
36
37
31 & 30
I
O
I
O
O
VREF
16 10 O
VREFI
15 9
I
L_FILT
21
15
I
R_FILT
19
13
I
NC 29 23
Description
24.576 MHz Crystal #1 Input.
24.576 MHz Crystal #1 Output.
16.9344 MHz Crystal #2 Input.
16.9344 MHz Crystal #2 Output.
External Control. These TTL signals reflect the current status of register bits inside the
AD1847. They can be used for signaling or to control external logic.
Voltage Reference. Nominal 2.25 volt reference available externally as a voltage datum
for dc-coupling and level-shifting. VREF should not have any signal dependent load.
Voltage Reference Internal. Voltage reference filter point for external bypassing only.
Left Channel Filter Capacitor. This pin requires a 1.0 µF capacitor to analog ground
for proper operation.
Right Channel Filter Capacitor. This pin requires a 1.0 µF capacitor to analog ground
for proper operation.
No Connect. Do not connect.
Power Supplies
Pin Name
PLCC
TQFP
I/O Description
VCC
GNDA
VDD
GNDD
13 & 25
14, 20, 24
2, 9, 34, 39
3, 10, 35, 38
7 & 19
8, 14, 18
40, 3, 28, 33
41, 4, 29, 32
I
I
I
I
Analog Supply Voltage (+5 V).
Analog Ground.
Digital Supply Voltage (+5 V).
Digital Ground.
(Continued from page 1)
The ∑∆ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images are removed from the DACs’
analog stereo output by on-chip switched-capacitor and
continuous-time filters. Two stereo pairs of auxiliary line-level
inputs can also be mixed in the analog domain with the DAC
output.
The AD1847 serial data interface uses a Time Division Multi-
plex (TDM) scheme that is compatible with DSP serial ports
configured in Multi-Channel Mode with 32 16-bit time slots
(i.e., SPORT0 on the ADSP-2101, ADSP-2115, etc.).
AUDIO FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD1847 and is
intended as a general introduction to the capabilities of the de-
vice. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.
Analog Inputs
The AD1847 SoundPort Stereo Codec accepts stereo line-level
inputs. All inputs should be capacitively coupled (ac-coupled) to
the AD1847. LINE1, LINE2, and AUX1, and post-mixed DAC
output analog stereo signals are multiplexed to the internal pro-
grammable gain amplifier (PGA) stage.
The PGA following the input multiplexer allows independent
selectable gains for each channel from 0 to 22.5 dB in +1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left-channel inputs appearing at
both channel outputs.
Analog Mixing
AUX1 and AUX2 analog stereo signals can be mixed in the ana-
log domain with the DAC output. Each channel of each auxil-
iary analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. The
post-mixed DAC output is available on L_OUT and R_OUT
externally and as an input to the ADCs.
Even if the AD1847 is not playing back data from its DACs, the
analog mix function can still be active.
Analog-to-Digital Datapath
The ∑∆ ADCs incorporate a proprietary fourth-order modula-
tor. A single pole of passive filtering is all that is required for
antialiasing the analog input because of the ADC’s high 64
times oversampling ratio. The ADCs include digital decimation
filters that low-pass filter the input to 0.4 ϫ FS. (“FS’’ is the
word rate or “sampling frequency.”) ADC input overrange con-
ditions will cause status bits to be set that can be read.
Digital-to-Analog Datapath
The ∑∆ DACs contain a programmable attenuator and a low-
pass digital interpolation filter. The anti-imaging interpolation
filter oversamples and digitally filters the higher frequency im-
ages. The attenuator allows independent control of each DAC
channel from 0 dB to –94.5 dB in 1.5 dB steps plus full mute.
The DACs’ ∑∆ noise shapers also oversample and convert the
signal to a single-bit stream. The DAC outputs are then filtered
in the analog domain by a combination of switched-capacitor
and continuous-time filters. These filters remove the very high
frequency components of the DAC bitstream output. No exter-
nal components are required.
REV. B
–7–

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