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AD1849 데이터시트 PDF




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부품번호 AD1849 기능
기능 Parallel-Port 16-Bit SoundPort Stereo Codec
제조업체 Analog Devices
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AD1849 데이터시트, 핀배열, 회로
a
Parallel-Port 16-Bit
SoundPort Stereo Codec
AD1848K
FEATURES
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System®
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
68-Lead PLCC and 68-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Supports One or Two DMA Channels and
Programmed I/O
PRODUCT OVERVIEW
The Parallel-Port AD1848K SoundPort® Stereo Codec inte-
grates the key audio data conversion and control functions into
a single integrated circuit. The AD1848K is intended to provide
a complete, single-chip audio solution for business audio and
multimedia applications requiring operation from a single +5 V
SoundPort is a registered trademark of Analog Devices, Inc.
supply. It provides a direct, byte-wide interface to both ISA
(“AT”) and EISA computer buses for simplified implementa-
tion on a computer motherboard or add-in card. The AD1848K
generates enable and direction controls for IC buffers such as
74_245.
The AD1848K SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control. Two
input control lines support mixed direct and indirect addressing
of twenty-one internal control registers over this asynchronous
interface.
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output fil-
ters are incorporated on-chip. Dynamic range exceeds 80 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.
The Codec includes a stereo pair of ∑∆ analog-to-digital
converters and a stereo pair of ∑∆ digital-to-analog converters.
Inputs to the ADC can be selected from four stereo pairs of
(Continued on page 9)
FUNCTIONAL BLOCK DIAGRAM
ANALOG
ANALOG
SUPPLY
DIGITAL
SUPPLY
CRYSTALS
22
POWER DOWN
DIGITAL
L_LINE
R_LINE
L_MIC
R_MIC
L_AUX1
R_AUX1
L_OUT
R_OUT
L_AUX2
R_AUX2
L
GAIN
20
dB MUX
R
GAIN
∑∆ A/D
CONVERTER
∑∆ A/D
CONVERTER
OSCILLATORS
16 µ/
A
L
16 A
W
GAIN/ATTEN/MUTE
L
ATTEN/
MUTE
R
ATTEN/
MUTE
ANALOG
FILTER
ANALOG
FILTER
∑∆ D/A
CONVERTER
∑∆ D/A
CONVERTER
DIGITAL
MIX
INTERPOL ATTENUATE
INTERPOL ATTENUATE
µ/
A
L
A
W
P
A
R
A
L
L
E
L
P
O
R
T
2
8
2
GAIN/ATTEN/MUTE
REFERENCE
CONTROL
REGS
2
PLAYBACK REQ
PLAYBACK ACK
CAPTURE REQ
CAPTURE ACK
ADR1:0
DATA7:0
CS
WR
RD
BUS DRIVER
CONTROL
HOST DMA
INTERRUPT
EXTERNAL
CONTROL
2.25V
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD1849 pdf, 반도체, 판매, 대치품
AD1848K
DAC ATTENUATOR
Step Size (0 dB to –34.5 dB)
Step Size (–60 dB to –94.5 dB)*
Output Attenuation Range Span*
ANALOG OUTPUT
Full-Scale Output Voltage
Output Impedance
External Load Impedance
Output Capacitance
External Load Capacitance
VREF
VREF Current Drive
VREF Output Impedance
Mute Attenuation of 0 dB
Fundamental* (OUT)
Mute Click
(|Muted Output Minus Unmuted
Midscale DAC Output|)
SYSTEM SPECIFICATIONS
Peak-to-Peak Frequency Response Ripple*
(Line In to Line Out)
Differential Nonlinearity*
Phase Linearity Deviation*
STATIC DIGITAL SPECIFICATIONS
Min
1.3
1.0
93.5
Min
1.85
10
2.10
Min
High Level Input Voltage (VIH)
Digital Inputs
XTAL1/2I
Low Level Input Voltage (VIL)
High Level Output Voltage (VOH) at IOH = –2 mA
Low Level Output Voltage (VOL) at IOL = 2 mA
Input Leakage Current
(GO/NOGO Tested)
Output Leakage Current
(GO/NOGO Tested)
Typ
1.5
1.5
94.5
Typ
0.707
2.0
2.25
100
4
Max
1.7
2.0
95.5
Max
2.1
600
15
100
2.40
–80
5
Typ
Min
2.4
2.4
–0.3
2.4
–10
–10
Max
1.0
±1
5
Max
(VD+) + 0 3
(VD+) + 0 3
0.8
0.4
10
10
Units
dB
dB
dB
Units
Vrms
V p-p
k
pF
pF
V
µA
k
dB
mV
Units
dB
Bit
Degrees
Units
V
V
V
V
V
µA
µA
–4– REV. 0

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AD1849 전자부품, 판매, 대치품
AD1848K
PIN DESCRIPTION
Parallel Interface
Pin Name PLCC
CDRQ
12
CDAK
PDRQ
11
14
PDAK
ADR1:0
13
9 & 10
RD 60
WR 61
CS 59
DATA7:0
DBEN
3–6 &
65–68
63
DBDIR
62
TQFP
3
I/O
O
2I
5O
4I
1 & 64 I
47 I
48 I
46 I
52–55 & I/O
58–61
50 O
49 O
Description
Capture Data Request. The assertion of this signal indicates that the Codec has a cap-
tured audio sample from the ADC ready for transfer. This signal will remain asserted un-
til all the bytes from the capture buffer have been transferred.
Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD
cycle occurring is a DMA read from the capture buffer.
Playback Data Request. The assertion of this signal indicates that the Codec is ready for
more DAC playback data. The signal will remain asserted until all the bytes needed for a
playback sample have been transferred.
Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR
cycle occurring is a DMA write to the playback buffer.
Codec Addresses. These address pins are asserted by the Codec interface logic during a
control register/PIO access. The state of these address lines determine which register is
accessed.
Read Command Strobe. This active LO signal defines a read cycle from the Codec. The
cycle may be a read from the control/PIO registers, or the cycles could be a read from the
Codec’s DMA sample registers.
Write Command Strobe. This active LO signal indicates a write cycle to the Codec. The
cycle may be a write to the control/PIO registers, or the cycle could be a write to the
Codec’s DMA sample registers.
AD1848K Chip Select. The Codec will not respond to any control/PIO cycle accesses
unless this active LO signal is LO. This signal is ignored during DMA transfers.
Data Bus. These pins transfer data and control information between the Codec and the
host.
Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.
For control register/PIO cycles,
DBEN = (WR or RD) and CS
For DMA cycles,
DBEN = (WR or RD) and (PDAK or CDAK)
Data Bus Direction. This pin controls the direction of the data bus transceiver. HI
enables writes from the host to the AD1848K; LO enables reads from the AD1848K to
the host bus. This signal is normally HI.
For control register/PIO cycles,
DBDIR = RD and CS
For DMA cycles,
DBDIR = RD and (PDAK or CDAK)
REV. 0
–7–

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