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AD1851 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD1851은 전자 산업 및 응용 분야에서
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부품번호 AD1851 기능
기능 16-Bit/18-Bit/ 16 X Fs PCM Audio DACs
제조업체 Analog Devices
로고 Analog Devices 로고


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AD1851 데이터시트, 핀배열, 회로
a
16-Bit/18-Bit, 16 ؋ FS
PCM Audio DACs
FEATURES
110 dB SNR
Fast Settling Permits 16؋ Oversampling
؎3 V Output
Optional Trim Allows Super-Linear Performance
؎5 V Operation
16-Pin Plastic DIP and SOIC Packages
Pin-Compatible with AD1856 & AD1860 Audio DACs
2s Complement, Serial Input
APPLICATIONS
High-End Compact Disc Players
Digital Audio Amplifiers
DAT Recorders and Players
Synthesizers and Keyboards
PRODUCT DESCRIPTION
The AD1851/AD1861 is a monolithic PCM audio DAC. The
AD1851 is a 16-bit device, while the AD1861 is an 18-bit de-
vice. Each device provides a voltage output amplifier, DAC,
serial-to-parallel register and voltage reference. The digital por-
tion of the AD1851/AD1861 is fabricated with CMOS logic
elements that are provided by Analog Devices’ 2 µm ABCMOS
process. The analog portion of the AD1851/AD1861 is fabri-
cated with bipolar and MOS devices as well as thin-film
resistors.
This combination of circuit elements, as well as careful design
and layout techniques, results in high performance audio play-
back. Laser-trimming of the linearity error affords low total har-
monic distortion. An optional linearity trim pin is provided to
allow residual differential linearity error at midscale to be elimi-
nated. This feature is particularly valuable for low distortion
reproductions of low amplitude signals. Output glitch is also
small, contributing to the overall high level of performance. The
output amplifier achieves fast settling and high slew rates, pro-
viding a full ± 3 V signal at load currents up to 8 mA. When
used in current output mode, the AD1851/AD1861 provides a
± 1 mA output signal. The output amplifier is short circuit
protected and can withstand indefinite shorts to ground.
The serial input interface consists of the clock, data and latch
enable pins. The serial 2s complement data word is clocked into
the DAC, MSB first, by the external clock. The latch enable
signal transfers the input word from the internal serial input
register to the parallel DAC input register. The AD1851 input
clock can support a 12.5 MHz data rate, while the AD1861 in-
put clock can support a 13.5 MHz data rate. This serial input
port is compatible with second generation digital filter chips
used in consumer audio products. These filters operate at over-
sampling rates of 2ϫ, 4ϫ, 8ϫ and 16ϫ sampling frequencies.
AD1851/AD1861
FUNCTIONAL BLOCK DIAGRAM
–VS 1
DGND 2
+VL 3
NC 4
CLK 5
LE 6
LATCH
DAC
SERIAL
INPUT
REGISTER
CONTROL
LOGIC
IOUT
DATA 7
NC 8
AD1851/
AD1861
NC = NO CONNECT
16 +VS
15 TRIM
14 MSB ADJ
13 IOUT
12 AGND
11 SJ
10 RF
9 VOUT
The critical specifications of THD+N and signal-to-noise ratio
are 100% tested for all devices.
The AD1851/AD1861 operates with ± 5 V power supplies, mak-
ing it suitable for home use markets. The digital supply, VL, can
be separated from the analog supplies, VS and –VS, for reduced
digital crosstalk. Separate analog and digital ground pins are
also provided. Power dissipation is 100 mW typical.
The AD1851/AD1861 is available in either a 16-pin plastic DIP
or a 16-pin plastic SOIC package. Both packages incorporate
the industry standard pinout found on the AD1856 and
AD1860 PCM audio DACs. As a result, the AD1851/AD1861
is a drop-in replacement for designs where ± 5 V supplies have
been used with the AD1856/AD1860. Operation is guaranteed
over the temperature range of –25°C to +70°C and over the
voltage supply range of ± 4.75 V to ± 5.25 V.
PRODUCT HIGHLIGHTS
l. AD1851 16-bit resolution provides 96 dB dynamic range.
AD1861 18-bit resolution provides 108 dB dynamic range.
2. No external components are required.
3. Operates with ± 5 V supplies.
4. Space saving 16-pin SOIC and plastic DIP packages.
5. 100 mW power dissipation.
6. High input clock data rates and 1.5 µs settling time permits
2ϫ, 4ϫ, 8ϫ and 16ϫ oversampling.
7. ± 3 V or ± 1 mA output capability.
8. THD + Noise and SNR are 100% tested.
9. Pin-compatible with AD1856 & AD1860 PCM audio DACs.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD1851 pdf, 반도체, 판매, 대치품
AD1851/AD1861
ABSOLUTE MAXIMUM RATINGS*
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –6.50 V to 0 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VL
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V
Short Circuit . . . . . . . . . . . . . . . . . Indefinite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . –60°C to +100°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Resolution
THD + N
AD1851N
AD1851N-J
AD1851R
AD1851R-J
AD1861N
AD1861N-J
AD1861R
AD1861R-J
16 Bits
16 Bits
16 Bits
16 Bits
18 Bits
18 Bits
18 Bits
18 Bits
0.008%
0.004%
0.008%
0.004%
0.008%
0.004%
0.008%
0.004%
*N = Plastic DIP Package; R = Small Outline (SOIC) Package.
Package
Option*
N-16
N-16
R-16
R-16
N-16
N-16
R-16
R-16
PIN DESCRIPTIONS
1 –VS
Analog Negative Power Supply
2 DGND Logic Ground
3 VL
4 NC
Logic Positive Power Supply
No Connection
5 CLK
Clock Input
6 LE
Latch Enable Input
7 DATA
Serial Data Input
8 NC
No Internal Connection*
9 VOUT
10 RF
11 SJ
Voltage Output
Feedback Resistor
Summing Junction
12 AGND
Analog Ground
13 IOUT
Current Output
14 MSB ADJ MSB Adjustment Terminal
15 TRIM
MSB Trimming Potentiometer Terminal
16 VS
Analog Positive Power Supply
*Pin 8 has no internal connection; -VL from AD1856 or AD1860 socket can be
safely applied.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.
WARNING!
ESD SENSITIVE DEVICE
Typical Performance
175
150
125
100
75
50
25
2
4
6
8
10 12
14
CLOCK FREQUENCY – MHz
Power Dissipation vs. Clock Frequency
10
1
–60dB
0.1
0.01
–20dB
0dB
0.001
–30 –20 –10 0 10 20 30 40 50 60 70 80 90
TEMPERATURE – °C
THD vs. Temperature
–4– REV. A

4페이지










AD1851 전자부품, 판매, 대치품
AD1851 DIGITAL CIRCUIT CONSIDERATIONS
AD1851 Input Data
Data is transmitted to the AD1851 in a bit stream composed of
16-bit words with a serial, MSB first format. Three signals
must be present to achieve proper operation. They are the
Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 16th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 5 illustrates the general signal require-
ments for data transfer to the AD1851.
CLOCK
DATA
M
S
B
L
S
B
LATCH
Figure 5. Signal Requirements for AD1851
Figure 6 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. The input pins of the AD1851 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Fig-
ures 5 and 6 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems.
The AD1851 input clock can run at a 12.5 MHz rate. This
clock rate will allow data transfer rates for 2ϫ, 4ϫ or 8ϫ or
16ϫ oversampling reconstructions.
>30ns
DATA
>15ns
>15ns
>40ns
CLOCK
>30ns
>30ns
>80.0ns
>15ns
LATCH
>40ns
>40ns
Figure 6. Timing Relationships of AD1851 Input Signals
AD1851/AD1861
AD1861 DIGITAL CIRCUIT CONSIDERATIONS
AD1861 Input Data
Data is transmitted to the AD1861 in a bit stream composed of
18-bit words with a serial, MSB first format. Three signals
must be present to achieve proper operation. They are the
Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 18th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 7 illustrates the general signal require-
ments for data transfer to the AD1861.
CLOCK
DATA
M
S
B
L
S
B
LATCH
Figure 7. Signal Requirements for AD1861
Figure 8 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. The input pins of the AD1861 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Fig-
ures 7 and 8 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems.
The AD1861 input clock can run at a 13.5 MHz rate. This
clock rate will allow data transfer rates for 2ϫ, 4ϫ or 8ϫ or
16ϫ oversampling reconstructions.
DATA
CLOCK
>30ns
>15ns
>15ns
>40ns
>30ns
>30ns
>74.1ns
>15ns
LATCH
>40ns
>40ns
Figure 8. Timing Relationships of AD1861 Input Signals
REV. A
–7–

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