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AD1853 데이터시트 PDF




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부품번호 AD1853 기능
기능 Stereo/ 24-Bit/ 192 kHz/ Multibit DAC
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AD1853 데이터시트, 핀배열, 회로
a Stereo, 24-Bit, 192 kHz, Multibit ⌺⌬ DAC
AD1853*
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Differential Output for Optimum Performance
120 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Mono)
117 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Stereo)
119 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Mono)
116 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
–107 dB THD+N (Mono Application Circuit, See Figure 30)
–104 dB THD+N (Stereo)
115 dB Stopband Attenuation (96 kHz)
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Interpolation Factor, Volume, Mute, De-Emphasis, Reset
Digital De-Emphasis Processing for 32, 44.1 and 48 kHz
Sample Rates
Clock Auto-Divide Circuit Supports Five Master-Clock
Frequencies
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive
Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1853 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a high per-
formance digital interpolation filter, a multibit sigma-delta
modulator, and a continuous-time current-out analog DAC
section. Other features include an on-chip clickless stereo at-
tenuator and mute capability, programmed through an SPI-
compatible serial control port. The AD1853 is fully compatible
with all known DVD formats and supports 48 kHz, 96 kHz and
192 kHz sample rates with up to 24 bits word lengths. It also
provides the “Redbook” standard 50 µs/15 µs digital de-emphasis
filters at sample rates of 32 kHz, 44.1 kHz and 48 kHz.
The AD1853 has a very flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers and sample rate converters. The
AD1853 can be configured in left-justified, I2S, right-justified,
or DSP serial port compatible modes. The AD1853 accepts
serial audio data in MSB first, twos complement format.
The AD1853 operates from a single +5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed in
a 28-lead SSOP package for operation over the temperature
range 0°C to +70°C.
FUNCTIONAL BLOCK DIAGRAM
INT2؋ INT4؋
CONTROL DATA
VOLUME INPUT
MUTE
3
DIGITAL
SUPPLY
2
CLOCK
IN
AD1853
SERIAL CONTROL
INTERFACE
VOLTAGE
REFERENCE
AUTO-CLOCK
DIVIDE CIRCUIT
DIGITAL
DATA INPUT
SERIAL 2
MODE
SERIAL
DATA
INTERFACE
ATTEN/
MUTE
ATTEN/
MUTE
8 ؋ FS
INTERPOLATOR
8 ؋ FS
INTERPOLATOR
MULTIBIT SIGMA-
DELTA MODULATOR
MULTIBIT SIGMA-
DELTA MODULATOR
IDAC
IDAC
ANALOG
OUTPUTS
*Patents Pending.
RESET
MUTE
DE-EMPHASIS
2
ANALOG
SUPPLY
2
ZERO
FLAG
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999




AD1853 pdf, 반도체, 판매, 대치품
AD1853
ABSOLUTE MAXIMUM RATINGS*
Min Max
Units
DVDD to DGND
AVDD to AGND
Digital Inputs
Analog Outputs
AGND to DGND
Reference Voltage
Soldering
–0.3
–0.3
DGND – 0.3
AGND – 0.3
–0.3
6
6
DVDD + 0.3
AVDD + 0.3
0.3
(AVDD + 0.3)/2
+300
10
V
V
V
V
V
°C
sec
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE CHARACTERISTICS
Min
θJA (Thermal Resistance
[Junction-to-Ambient])
θJC (Thermal Resistance
[Junction-to-Case])
Typ
109
39
Max Units
°C/W
°C/W
PIN CONFIGURATION
DGND 1
28 DVDD
MCLK 2
27 SDATA
CLATCH 3
26 BCLK
CCLK 4
25 L/RCLK
CDATA 5
24 RST
INT4؋ 6
23 MUTE
AD1853
INT2؋ 7 TOP VIEW 22 ZEROL
ZEROR 8 (Not to Scale) 21 IDPM0
DEEMP 9
20 IDPM1
IREF 10
19 FILTB
AGND 11
18 AVDD
OUTL+ 12
17 OUTR+
OUTL– 13
16 OUTR–
FILTR 14
15 FCR
Model
AD1853JRS
AD1853JRSRL
Temperature
0°C to +70°C
0°C to +70°C
ORDERING GUIDE
Package Description
28-Lead Shrink Small Outline
28-Lead Shrink Small Outline
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Package Options
RS-28
RS-28 on 13" Reels
WARNING!
ESD SENSITIVE DEVICE
–4– REV. A

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AD1853 전자부품, 판매, 대치품
AD1853
OPERATING FEATURES
Serial Data Input Port
The AD1853’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero
(default at power-up). To control the serial mode using the SPI
mode select bits, the external mode control pins should be
grounded.
In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24 (extra
bits will not cause an error, but they will be truncated inter-
nally). In the right-justified mode, control register Bits 8 and 9
are used to set the word length to 16, 20, or 24 bits. The default
on power-up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4 and 5) should be tied LO.
Serial Data Input Mode
The AD1853 uses two multiplexed input pins to control the
mode configuration of the input data port mode.
IDPM1
(Pin 20)
0
0
1
1
Table I. Serial Data Input Modes
IDPM0
(Pin 21)
0
1
0
1
Serial Data Input Format
Right Justified (24 Bits) Default
I2S-Compatible
Left Justified
DSP
Figure 1 shows the right-justified mode. LRCLK is HI for the
left channel, LO for the right channel. Data is valid on the rising
edge of BCLK.
In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI word length control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial
port will begin to accept data starting at the 8th bit clock pulse
after the L/RCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 16-bit mode, data is accepted starting at the
16th-bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore other data formats
are possible using the delay values described above. For detailed
timing, see Figure 6.
Figure 2 shows the I2S mode. L/RCLK is LO for the left chan-
nel, and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an L/RCLK transi-
tion but with a single BCLK period delay. The I2S mode can be
used to accept any number of bits up to 24.
Figure 3 shows the left-justified mode. L/RCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/RCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.
Figure 4 shows the DSP serial port mode. L/RCLK must pulse
HI for at least one bit clock period before the MSB of the left
channel is valid, and L/RCLK must pulse HI again for at least
one bit clock period before the MSB of the right channel is
valid. Data is valid on the falling edge of BCLK. The DSP serial
port mode can be used with any word length up to 24 bits.
BCLK
L/RCLK
tDBH
tDBL
tDLS
tDBP
SDATA
LEFT-JUSTIFIED
MODE
SDATA
I2S-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
tDDS
MSB
tDDH
MSB-1
tDDS
MSB
tDDH
8-BIT CLOCKS
(24-BIT DATA)
tDDS
MSB
tDDH
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 6. Serial Data Port Timing
tDDS
LSB
tDDH
REV. A
7

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