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AD1855 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD1855은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AD1855 자료 제공

부품번호 AD1855 기능
기능 Stereo/ 96 kHz/ Multibit DAC
제조업체 Analog Devices
로고 Analog Devices 로고


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AD1855 데이터시트, 핀배열, 회로
a
Stereo, 96 kHz, Multibit ⌺⌬ DAC
AD1855*
FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulator with “Perfect Differen-
tial Linearity Restoration” for Reduced Idle Tones
and Noise Floor
Data Directed Scrambling DAC—Least Sensitive to
Jitter
Differential Output for Optimum Performance
113 dB Signal-to-Noise and Dynamic Range at 48 kHz
Sample Rate
110 dB Signal-to-Noise and Dynamic Range at 96 kHz
Sample Rate
–97 dB THD+N
On-Chip Volume Control with 1024 Steps
Hardware and Software Controllable Clickless Mute
Zero Input Flag Outputs for Left and Right Channels
Digital De-Emphasis Processing
Supports 128, 256, 384, and 512 ؋ FS Master Mode
Clock
Switchable Clock Doubler
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Set-Top Boxes, Home Theater Systems, Auto-
motive Audio Systems, Computer Multimedia Prod-
ucts, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEW
The AD1855 is a high performance, single-chip stereo, audio
DAC delivering 113 dB Dynamic Range and SNR (A-weighted—
not muted) at 48 kHz sample rate. It is comprised of a multibit
sigma-delta modulator with dither, continuous time analog
filters and analog output drive circuitry. Other features include
an on-chip stereo attenuator and mute, programmed through an
SPI-compatible serial control port. The AD1855 is fully com-
patible with current DVD formats, including 96 kHz sample
frequency and 24 bits. It is also backwards compatible by sup-
porting 50 µs/15 µs digital de-emphasis intended for “redbook”
44.1 kHz sample frequency playback from compact discs.
The AD1855 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The AD1855 can be configured in left-justified, I2S, right-
justified, or DSP serial port compatible modes. The AD1855
accepts 16-/18-/20-/24-bit serial audio data in MSB first, twos-
complement format. A power-down mode is offered to mini-
mize power consumption when the device is inactive. The
AD1855 operates from a single +5 V power supply. It is fabri-
cated on a single monolithic integrated circuit and housed in a
28-lead SSOP package for operation over the temperature range
0°C to +70°C.
FUNCTIONAL BLOCK DIAGRAM
CONTROL DATA
VOLUME INPUT
MUTE
3
DIGITAL
SUPPLY
CLOCK
IN
96/48FS
CLOCK
2
AD1855
SERIAL CONTROL VOLTAGE
INTERFACE
REFERENCE
CLOCK
CIRCUIT
384/ 256
X2MCLK
16-/18-/20-/24-BIT 3
DIGITAL
DATA INPUT
SERIAL 2
MODE
SERIAL
DATA
INTERFACE
ATTEN/
MUTE
ATTEN/
MUTE
PD /RST
8؋
INTERPOLATOR
8؋
INTERPOLATOR
MUTE
MULTIBIT SIGMA-
DELTA MODULATOR
MULTIBIT SIGMA-
DELTA MODULATOR
DAC
DAC
DE-EMPHASIS
2
ANALOG
SUPPLY
OUTPUT
BUFFER
OUTPUT
BUFFER
2
ZERO
FLAG
ANALOG
OUTPUTS
*Patents Pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000




AD1855 pdf, 반도체, 판매, 대치품
AD1855
ABSOLUTE MAXIMUM RATINGS*
Min Max
Units
DVDD to DGND
AVDD to AGND
Digital Inputs
Analog Outputs
AGND to DGND
Reference Voltage
Soldering
–0.3
–0.3
DGND – 0.3
AGND – 0.3
–0.3
6
6
DVDD + 0.3
AVDD + 0.3
0.3
(AVDD + 0.3)/2
+300
10
V
V
V
V
V
°C
sec
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE CHARACTERISTICS
Min
θJA (Thermal Resistance
[Junction-to-Ambient])
θJC (Thermal Resistance
[Junction-to-Case])
Typ
109
39
Max Units
°C/W
°C/W
PIN CONFIGURATION
DGND 1
28 DVDD
MCLK 2
27 SDATA
CLATCH 3
CCLK 4
26 BCLK
25 L/RCLK
CDATA 5
24 PD/RST
384/256
X2MCLK
ZEROR
6 AD1855 23 MUTE
7 TOP VIEW 22 ZEROL
8 (Not to Scale) 21 IDPM0
DEEMP 9
96/48 10
20 IDPM1
19 FILTB
AGND 11
18 AVDD
OUTR+ 12
17 OUTL+
OUTR– 13
16 OUTL–
FILTR 14
15 AGND
Model
AD1855JRS
AD1855JRSRL
Temperature
0°C to +70°C
0°C to +70°C
ORDERING GUIDE
Package Description
28-Lead Shrink Small Outline
28-Lead Shrink Small Outline
Package Options
RS-28
RS-28 on 13Reels
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1855 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. B

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AD1855 전자부품, 판매, 대치품
AD1855
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB MSB1 MSB2
LSB+2 LSB+1 LSB
MSB MSB1 MSB2
Figure 1. Right-Justified Mode
LSB+2 LSB+1 LSB
MSB
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB MSB1 MSB2
LSB+2 LSB+1 LSB
MSB MSB1 MSB2
Figure 2. I2S-Justified Mode
LSB+2 LSB+1 LSB
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB MSB1 MSB2
LSB+2 LSB+1 LSB
MSB MSB1 MSB2
Figure 3. Left-Justified Mode
LSB+2 LSB+1 LSB
MSB
MSB MSB1
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB MSB1
LSB+2 LSB+1 LSB
MSB MSB1
LSB+2 LSB+1 LSB
Figure 4. Left-Justified DSP Mode
MSB MSB1
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
LSB
MSB MSB1 MSB2
RIGHT CHANNEL
LSB+2 LSB+1 LSB
MSB MSB1 MSB2
Figure 5. 32 × FS Packed Mode
LSB+2 LSB+1 LSB
MSB MSB1
REV. B
–7–

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