AD1857 Datasheet PDF - Analog Devices
| Part Number | AD1857 | |
| Description | Stereo/ Single Supply 16-/ 18- and 20-Bit Sigma-Delta DACs | |
| Manufacturers | Analog Devices | |
| Logo |  |
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a
Stereo, Single Supply
16-, 18- and 20-Bit Sigma-Delta DACs
AD1857/AD1858
FEATURES
Low Cost, High Performance Stereo DACs
128 Times Oversampling Interpolation Filter
Multibit ⌺⌬ Modulator with Triangular PDF Dither
Discrete Time and Continuous Time Analog
Reconstruction Filters
Extremely Low Out-of-Band Energy
Buffered Outputs with 2 k⍀ Output Load Drive
94 dB Dynamic Range, –90 dB THD+N Performance
Digital De-emphasis and Mute
؎0.1؇C Maximum Phase Linearity Deviation
Continuously Variable Sample Rate Support
Power-Down Mode
16-, 18- and 20-Bit I2S-Justified, Left-Justified Modes
Offered on AD1857
Accepts 24-Bit Word
16-Bit Right-Justified and DSP Serial Port Modes
Offered on AD1858
Single +5 V Supply
20-Pin SSOP Package
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Video Laser Disk, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC and MD Players
Digital Audio Workstations, Computer Multimedia
Products
PRODUCT OVERVIEW
The AD1857/AD1858 are complete single-chip stereo digital
audio playback components. They each comprise an advanced
digital interpolation filter, a revolutionary “linearity-compensated”
multibit sigma-delta (∑∆) modulator with dither, a jitter-tolerant
DAC, switched capacitor and continuous time analog filters and
analog output drive circuitry. Other features include digital
de-emphasis processing and mute. The AD1857/AD1858
support continuously variable sample rates with essentially
linear phase response, and support 50/15 µs digital de-emphasis
intended for “Redbook” 44.1 kHz sample frequency playback
from Compact Discs. The user must provide a master clock that
is synchronous with the left/right clock at 256 or 384 times the
intended sample frequency.
The AD1857/AD1858 have a simple but very flexible serial data
input port that allows for glueless interconnection to a variety of
ADCs, DSP chips, AES/EBU receivers and sample rate con-
verters. The AD1857 serial data input port can be configured
in either 16-bit, 18-bit or 20-bit left-justified or I2S-justified
modes. The AD1858 serial data input port can be configured in
either 16-bit right-justified or DSP serial port compatible modes.
The AD1857/AD1858 accept serial audio data in MSB first,
twos-complement format. A power-down mode is offered to
minimize power consumption when the device is inactive. The
AD1857/AD1858 operate from a single +5 V power supply.
They are fabricated on a single monolithic integrated circuit and
housed in 20-pin SSOP packages for operation over the
temperature range 0°C to +70°C.
DIGITAL
SUPPLY
2
FUNCTIONAL BLOCK DIAGRAM
COMMON
MODE
CLOCK CLOCK
MODE
IN
16-/18-/20-BIT
DIGITAL 3
DATA INPUT
SERIAL DATA
INTERFACE
AD1857/AD1858
VOLTAGE
REFERENCE
CLOCK
CIRCUIT
SERIAL
MODE
128x
INTERPOLATION
FILTER
128x
INTERPOLATION
FILTER
MUTE
MUTE
MULTIBIT
Σ∆ MODULATOR
MULTIBIT
Σ∆ MODULATOR
DAC
DAC
ANALOG
FILTER
ANALOG
FILTER
OUTPUT
BUFFER
OUTPUT
BUFFER
ANALOG
OUTPUTS
DE-EMPHASIS
MUTE
POWER-DOWN/RESET
4
ANALOG
SUPPLY
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
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AD1857/AD1858
PIN LIST
Digital Audio Serial Input Interfaces
Pin Name
Number
I/O
SDATA
20
I
BCLK
19
I
LRCLK
MODE
18
3
I
I
Description
Serial input, MSB first, containing two channels of 16, 18 or 20 bits (AD1857) or
16 bits (AD1858) of twos complement data per channel.
Bit clock input for input data. Need not run continuously; may be gated or used in a
burst fashion.
Left/right clock input for input data. Must run continuously.
Input serial data port mode control. Selects between I2S-justified (HI) and left-justified
(LO) on the AD1857. Selects between DSP serial port style mode (HI) and right-
justified (LO) on the AD1858. The state of the mode pin should be changed only when
the AD1857/AD1858 is held in reset (PD/RST LO). Otherwise, the AD1857/
AD1858 serial port may lose synchronism.
Control and Clock Signals
Pin Name
Number
I/O Description
PD/RST
DEEMP
MUTE
MCLK
384/256
2
5
15
1
6
I Power-Down/Reset. The AD1857/AD1858 are placed in a low power consumption
“sleep” mode when this pin is held LO. The AD1857/AD1858 are reset on the
rising edge of this signal. Connect HI for normal operation.
I De-emphasis. Digital de-emphasis is enabled when this input signal is HI. This is
used to impose a 50/15 µs response characteristic on the output audio spectrum at
an assumed 44.1 kHz sample rate.
I Mute. Assert HI to mute both stereo analog outputs of the AD1857/AD1858.
Deassert LO for normal operation.
I Master Clock Input. Connect to an external clock source at either 256 or 384 times
the intended sample frequency as determined by the 384/256 pin. Must be synchro-
nous with LRCLK, but may have any phase with respect to LRCLK.
I Selects the master clock mode as either 384 times the intended sample frequency
(HI) or 256 times the intended sample frequency (LO). The state of this input
should be hardwired to logic LO or logic HI or may be changed while the AD1857/
AD1858 is in power-down/reset. It must not be changed while the AD1857/AD1858
is operational.
Analog Signals
Pin Name
Number
I/O
Description
FILT
CMOUT
11
10
OUTL
OUTR
8
13
O Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage
reference with parallel 10 µF and 0.1 µF capacitors to the AGND pin.
O Voltage Reference Common Mode Output. Should be decoupled with 10 µF
capacitor to the AGND pin or plane. This output is available externally for dc
coupling and level-shifting. CMOUT should not have any signal dependent load,
or used where it will sink or source current.
O Left channel line level analog output.
O Right channel line level analog output.
Power Supply Connections and Miscellaneous
Pin Name
Number
I/O Description
AVDD
AGND
DVDD
DGND
N/C
7, 14
9, 12
17
16
4
I Analog Power Supply. Connect to analog +5 V supply.
I Analog Ground.
I Digital Power Supply. Connect to digital +5 V supply.
I Digital Ground.
No Connect. Reserved. Do not connect.
REV. 0
–5–
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| Information | Total 16 Pages | |
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| Download | [ AD1857.PDF Datasheet ] | |
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