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PDF AD1859 Data sheet ( Hoja de datos )
| Número de pieza | AD1859 | |
| Descripción | Stereo/ Single-Supply 18-Bit Integrated DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Stereo, Single-Supply
18-Bit Integrated ⌺⌬ DAC
AD1859
FEATURES
Complete, Low Cost Stereo DAC System in a Single Die
Package
Variable Rate Oversampling Interpolation Filter
Multibit ⌺⌬ Modulator with Triangular PDF Dither
Discrete and Continuous Time Analog Reconstruction
Filters
Extremely Low Out-of-Band Energy
64 Step (1 dB/Step) Analog Attenuator with Mute
Buffered Outputs with 2 k⍀ Output Load Drive
Rejects Sample Clock Jitter
94 dB Dynamic Range, –88 dB THD+N Performance
Option for Analog De-emphasis Processing with
External Passive Components
؎0.1؇ Maximum Phase Linearity Deviation
Continuously Variable Sample Rate Support
Digital Phase Locked Loop Based Asynchronous Master
Clock
On-Chip Master Clock Oscillator, Only External Crystal
Is Required
Power-Down Mode
Flexible Serial Data Port (I2S-Justified, Left-Justified,
Right-Justified and DSP Serial Port Modes)
SPI* Compatible Serial Control Port
Single +5 V Supply
28-Pin SOIC and SSOP Packages
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Digital Video Disc, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players
Digital Audio Workstations, Computer Multimedia
Products
PRODUCT OVERVIEW
The AD1859 is a complete 16-/18-bit single-chip stereo digital
audio playback subsystem. It comprises a variable rate digital
interpolation filter, a revolutionary multibit sigma-delta (∑∆)
modulator with dither, a jitter-tolerant DAC, switched capacitor
and continuous time analog filters, and analog output drive cir-
cuitry. Other features include an on-chip stereo attenuator and
mute, programmed through an SPI-compatible serial control
port.
The key differentiating feature of the AD1859 is its asynchro-
nous master clock capability. Previous ∑∆ audio DACs re-
quired a high frequency master clock at 256 or 384 times the
intended audio sample rate. The generation and management
of this high frequency synchronous clock is burdensome to the
board level designer. The analog performance of conventional
single bit ∑∆ DACs is also dependent on the spectral purity of
the sample and master clocks. The AD1859 has a digital Phase
Locked Loop (PLL) which allows the master clock to be asyn-
chronous, and which also strongly rejects jitter on the sample
clock (left/right clock). The digital PLL allows the AD1859 to
be clocked with a single frequency (27 MHz for example) while
the sample frequency (as determined from the left/right clock)
can vary over a wide range. The digital PLL will lock to the
new sample rate in approximately 100 ms. Jitter components
15 Hz above and below the sample frequency are rejected by
6 dB per octave. This level of jitter rejection is unprecedented
in audio DACs.
The AD1859 supports continuously variable sample rates with
essentially linear phase response, and with an option for external
analog de-emphasis processing. The clock circuit includes an
on-chip oscillator, so that the user need only provide an external
crystal. The oscillator may be overdriven, if desired, with an ex-
ternal clock source.
(continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
SUPPLY
2
CONTROL
DATA
INPUT
3
REFERENCE
FILTER AND
GROUND
2
ASYNCHRONOUS
CLOCK/CRYSTAL
16- OR 18-BIT 6
DIGITAL DATA
INPUT
AD1859
SERIAL
DATA
INTERFACE
VARIABLE RATE
INTERPOLATION
VARIABLE RATE
INTERPOLATION
POWER
DOWN/RESET
SERIAL
CONTROL
INTERFACE
VOLTAGE
REFERENCE
MULTIBIT
∑∆ MODULATOR
DAC
ANALOG
FILTER
MULTIBIT
∑∆ MODULATOR
DAC
ANALOG
FILTER
MUTE
DE-EMPHASIS
DPLL/CLOCK
MANAGER
ATTEN/
MUTE
ATTEN/
MUTE
OUTPUT
BUFFER
OUTPUT
BUFFER
2
ANALOG
SUPPLY
DE-EMPHASIS
SWITCH LEFT
COMMON MODE
ANALOG
OUTPUTS
DE-EMPHASIS
SWITCH RIGHT
*SPI is a registered trademark of Motorola, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD1859
DEFINITIONS
Dynamic Range
The ratio of a full-scale output signal to the integrated output
noise in the passband (0 to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is
equal to (S/[THD+N]) + 60 dB. Note that spurious harmonics
are below the noise with a –60 dB input, so the noise level es-
tablishes the dynamic range. This measurement technique is
consistent with the recommendations of the Audio Engineering
Society (AES17-1991) and the Electronics Industries Association
of Japan (EIAJ CP-307).
Total Harmonic Distortion + Noise (THD+N)
The ratio of the root-mean-square (rms) value of a full-scale
fundamental input signal to the rms sum of all other spectral
components in the passband, expressed in decibels (dB) and
percentage.
Passband
The region of the frequency spectrum unaffected by the attenu-
ation of the digital interpolation filter.
Passband Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the passband, ex-
pressed in decibels.
Stopband
The region of the frequency spectrum attenuated by the digi-
tal interpolation filter to the degree specified by “stopband
attenuation.”
Gain Error
With a near full-scale input, the ratio of actual output to ex-
pected output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ method)
Ratio of response on one channel with a zero input to a full-scale
1 kHz sine-wave input on the other channel, expressed in decibels.
Interchannel Phase Deviation
Difference in output sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.
Power Supply Rejection
With zero input, signal present at the output when a 300 mV
p-p signal is applied to power supply pins, expressed in decibels
of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to ap-
pear at the converter’s output, expressed in seconds (s). More
precisely, the derivative of radian phase with respect to radian
frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the passband, expressed in microseconds (µs).
PIN DESCRIPTIONS
Digital Audio Serial Input Interface
Serial Control Port Interface
Pin Name Number I/O Description
Pin Name Number I/O Description
SDATA 12
BCLK 14
LRCLK 13
IDPM0 9
IDPM1 10
18/16
8
I Serial input, MSB first, contain- CDATA 20
ing two channels of 16 or 18 bits
of twos complement data per
channel.
I Bit clock input for input data.
Need not run continuously; may CCLK
be gated or used in a burst
fashion.
19
I Left/right clock input for input
data. Must run continuously.
I Input serial data port mode
control zero. With IDPM1,
defines one of four serial input
modes.
CLATCH 21
I Input serial data port mode con-
trol one. With IDPM0, defines
one of four serial input modes.
I 18-bit or 16-bit input data mode
control. Connect this signal HI
for 18-bit input mode, LO for
16-bit input mode.
I Serial control input, MSB first,
containing 8 bits of unsigned
data per channel. Used for
specifying channel specific
attenuation and mute.
I Control clock input for control
data. Control input data must
be valid on the rising edge of
CCLK. CCLK may be continu-
ous or gated.
I Latch input for control data. This
input is rising edge sensitive.
REV. A
–5–
5 Page 
AD1859
AD1859 has been designed to minimize pops and clicks when
muting and unmuting the device. The AD1859 includes a zero
crossing detector which attempts to implement attenuation
changes on waveform zero crossings only. If a zero crossing is
not found within 1024 input sample periods (approximately
23 ms at 44.1 kHz), the attenuation change is made regardless.
Output Drive, Buffering and Loading
The AD1859 analog output stage is able to drive a 2 kΩ load. If
lower impedance loads must be driven, an external buffer stage
such as the Analog Devices SSM2142 should be used. The
analog output is generally ac coupled with a 10 µF capacitor,
even if the optional de-emphasis circuit is not used, as shown in
Figure 17. It is possible to dc couple the AD1859 output into an
op amp stage using the CMOUT signal as a bias point.
On-Chip Voltage Reference
The AD1859 includes an on-chip voltage reference that estab-
lishes the output voltage range. The nominal value of this refer-
ence is +2.25 V which corresponds to a line output voltage
swing of 3 V p-p. The line output signal is centered around a
voltage established by the CMOUT (common mode) output
(Pin 1). The reference must be bypassed both on the FILT in-
put (Pin 28) with 10 µF and 0.1 µF capacitors, and on the
CMOUT output (Pin 1) with a 10 µF and 0.1 µF capacitors, as
shown in Figures 17 and 18. The FILT pin must use the
FGND ground, and the CMOUT pin must use the AGND
ground. The on-chip voltage reference may be overdriven with
an external reference source by applying this voltage to the
FILT pin. CMOUT and FILT must still be bypassed as shown
in Figures 17 and 18. An external reference can be useful to
calibrate multiple AD1859 DACs to the same gain. Reference
bypass capacitors larger than those suggested can be used to im-
prove the signal-to-noise performance of the AD1859.
Power Down and Reset
The PD/RST input (Pin 11) is used to control the power con-
sumed by the AD1859. When PD/RST is held LO, the AD1859
is placed in a low dissipation power-down state. When PD/RST
is brought HI, the AD1859 becomes ready for normal operation.
The master clock (XTALI/MCLK, Pin 16) must be running for
a successful reset or power-down operation to occur. The PD/RST
signal must be LO for a minimum of four master clock periods
(approximately 150 ns with a 27 MHz XTALI/MCLK
frequency).
When the PD/RST input (Pin 11) is asserted brought HI, the
AD1859 is reset. All registers in the AD1859 digital engine (se-
rial data port, interpolation filter and modulator) are zeroed, and
the amplifiers in the analog section are shorted during the reset
operation. The two registers in the serial control port are initial-
ized to their default values. The user should wait 100 ms after
bringing PD/RST HI before using the serial data input port and
the serial control input port in order for the digital phase locked
loop to re-acquire lock. The AD1859 has been designed to
minimize pops and clicks when entering and exiting the power-
down state.
Control Signals
The IDPM0, IDPM1, 18/16, and DEEMP control inputs are
normally connected HI or LO to establish the operating state of
the AD1859. They can be changed dynamically (and asynchro-
nously to the LRCLK and the master clock) as long as they are
stable before the first serial data input bit (i.e., the MSB) is pre-
sented to the AD1859.
APPLICATIONS ISSUES
Interface to MPEG Audio Decoders
Figure 11 shows the suggested interface to the Analog Devices
ADSP-21xx family of DSP chips, for which several MPEG
audio decode algorithms are available. The ADSP-21xx supports
16 bits of data using a left-justified DSP serial port style format.
ADSP-21xx
SCLK
RFS
TFS
DT
DR
NC
NC
14 BCLK
13 LRCLK
12 SDATA AD1859
HI 9 IDPM0
HI 10 IDPM1
LO 8 18/16
Figure 11. Interface to ADSP-21xx
Figure 12 shows the suggested interface to the Texas Instru-
ments TMS320AV110 MPEG audio decoder IC. The
TMS320AV110 supports 18 bits of data using a right-justified
output format.
TEXAS
INSTRUMENTS
TMS320AV110
SCLK
LRCLK
PCMDATA
14 BCLK
13 LRCLK
12 SDATA
AD1859
PCMCLK
LO 9 IDPM0
48 x FS
LO 10 IDPM1
TO HI 8 18/16
1536 x FS
Figure 12. Interface to TMS320AV110
Figure 13 shows the suggested interface to the LSI Logic L64111
MPEG audio decoder IC. The L64111 supports 16 bits of data
using a left-justified output format.
LSI LOGIC
L64111
SCLKO
LRCLKO
SERO
SYSCLK
14 BCLK
13 LRCLK
12 SDATA AD1859
LO 9 IDPM0
384 x FS
HI 10 IDPM1
OR
512 x FS
LO
8 18/16
Figure 13. Interface to L64111
Figure 14 shows the suggested interface to the Philips SAA2500
MPEG audio decoder IC. The SAA2500 supports 18 bits of
data using an I2S compatible output format.
PHILIPS
SAA2500
SCK
WS
SD
FSCLKIN
256 x FS
OR
384 x FS
14 BCLK
13 LRCLK
12 SDATA AD1859
HI 9 IDPM0
LO 10 IDPM1
HI 8 18/16
Figure 14. Interface to SAA2500
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD1859.PDF ] | |
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