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PDF AD1868 Data sheet ( Hoja de datos )
| Número de pieza | AD1868 | |
| Descripción | Single Supply Dual 18-Bit Audio DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Single Supply
Dual 18-Bit Audio DAC
AD1868*
FEATURES
Dual Serial Input, Voltage Output DACs
Single +5 V Supply
0.004% THD+N (typ)
Low Power: 50 mW (typ)
108 dB Channel Separation (min)
Operates at 8؋ Oversampling
16-Pin Plastic DIP or SOIC Package
APPLICATIONS
Portable Compact Disc Players
Portable DAT Players and Recorders
Automotive Compact Disc Players
Automotive DAT Players
Multimedia Workstations
PRODUCT DESCRIPTION
The AD1868 is a complete dual 18-bit DAC offering excellent
performance while requiring a single +5 V power supply. It is
fabricated on Analog Devices’ ABCMOS wafer fabrication pro-
cess. The monolithic chip includes CMOS logic elements, bipo-
lar and MOS linear elements, and laser-trimmed thin-film
resistor elements. Careful design and layout techniques have re-
sulted in low distortion, low noise, high channel separation, and
low power dissipation.
The DACs on the AD1868 chip employ a partially segmented
architecture. The first three MSBs of each DAC are segmented
into seven elements. The 15 LSBs are produced using standard
R-2R techniques. The segments and R-2R resistors are laser
trimmed to provide extremely low total harmonic distortion.
The AD1868 requires no deglitcher or trimming circuitry. Low
noise is achieved through the use of two noise-reduction capacitors.
Each DAC is equipped with a high performance output ampli-
fier. These amplifiers achieve fast settling and high slew rate,
producing ± 1 V signals at load currents up to ± 1 mA. The
buffered output signal range is 1.5 V to 3.5 V. Reference volt-
ages of 2.5 V are provided, eliminating the need for “False
Ground” networks.
A versatile digital interface allows the AD1868 to be directly
connected to all digital filter chips. Fast CMOS logic elements
allow for an input clock rate of up to 13.5 MHz. This allows for
operation at 2×, 4×, 8×, or 16× the sampling frequency for each
channel. The digital input pins of the AD1868 are TTL and
+5 V CMOS compatible.
*Protected by U.S. Patent Numbers: 3,961,326; 4,141,004; 4,349,811;
4,857,862; and patents pending.
FUNCTIONAL BLOCK DIAGRAM
VL 1
LL 2
DL 3
CK 4
DR 5
LR 6
DGND 7
VBR 8
18-BIT
DAC
18-BIT
SERIAL
REGISTER
18-BIT
SERIAL
REGISTER
18-BIT
DAC
AD1868
16 VBL
–
+
VREF
15 VS
14 VOL
13 NRL
VREF
+
–
12 AGND
11 NRR
10 VOR
9 VS
The AD1868 operates on +5 V power supplies. The digital sup-
ply, VL, can be separated from the analog supply, VS, for re-
duced digital feedthrough. Separate analog and digital ground
pins are also provided. In systems employing a single +5 volt
power supply, VL and VS should be connected together. In bat-
tery operated systems, operation will continue even with reduced
supply voltage. Typically, the AD1868 dissipates 50 mW.
The AD1868 is packaged in either a 16-pin plastic DIP or a 16-
pin plastic SOIC package. Operation is guaranteed over the tem-
perature range of –35°C to +85°C and over the voltage supply
range of 4.75 V to 5.25 V.
PRODUCT HIGHLIGHTS
1. Single-supply operation @ +5 V.
2. 50 mW power dissipation (typical).
3. THD+N is 0.004% (typical).
4. Signal-to-Noise Ratio is 97.5 dB (typical).
5. 108 dB channel separation (minimum).
6. Compatible with all digital filter chips.
7. 16-pin DIP and 16-pin SOIC packages.
8. No deglitcher required.
9. No external adjustments required.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD1868
VL 1
LL 2
DL 3
CK 4
DR 5
LR 6
DGND 7
VBR 8
18-BIT
DAC
18-BIT
SERIAL
REGISTER
18-BIT
SERIAL
REGISTER
18-BIT
DAC
AD1868
16 VBL
–
+
VREF
15 VS
14 VOL
13 NRL
VREF
+
–
12 AGND
11 NRR
10 VOR
9 VS
DAC, the AD1868 can continue to function at supply voltages
as low as 3.5 V. Because of its unique design, the power require-
ments of the AD1868 diminish as the battery voltage drops, fur-
ther extending the operating time of the system.
POWER
SUPPLY
0.1µF
AD1868
1 VL
VBL 16
2 LL
VS 15
3 DL
VOL 14 4.7µF
4 CK
NRL 13
5 DR
6 LR
7 DGND
8 VBR
AGND 12
NRR 11
VOR 10 4.7µF
VS 9
0.1µF
Functional Block Diagram
ANALOG CIRCUIT CONSIDERATIONS
GROUNDING RECOMMENDATIONS
The AD1868 has two ground pins, designated as AGND (Pin
12) and DGND (Pin 7). The analog ground, AGND, serves as
the “high quality” reference ground for analog signals and as a
return path for the supply current from the analog portion of the
device. The system analog common should be located as close
as possible to Pin 12 to minimize any voltage drop which may
develop between these two points, although the internal circuit
is designed to minimize signal dependence of the analog return
current.
The digital ground, DGND, returns ground current from the
digital logic portion of the device. This pin should be connected
to the digital common node in the system. As shown in Figure
7, the analog and digital grounds should be joined at one point
in the system. When these two grounds are remotely connected
such as at the power supply ground, care should be taken to
minimize the voltage difference between the DGND and AGND
pins in order to ensure the specified performance.
POWER SUPPLIES AND DECOUPLING
The AD1868 has three power supply input pins. VS (Pins 9 and
15) provides the supply voltages which operate the analog por-
tion of the device including the 18-bit DACs, the voltage refer-
ences, and the output amplifiers. The VS supplies are designed
to operate with a +5 V supply. These pins should be decoupled
to analog common using a 0.1 µF capacitor. Good engineering
practice suggests that the bypass capacitors be placed as close as
possible to the package pins. This minimizes the inherent induc-
tive effects of printed circuit board traces.
VL (Pin 1) operates the digital portions of the chip including the
input shift registers and the input latching circuitry. VL is also
designed to operate with a +5 V supply. This pin should be by-
passed to digital common using a 0.1 µF capacitor, again placed
as close as possible to the package pin. Figure 7 illustrates the cor-
rect connection of the digital and analog supply bypass capacitors.
An important feature of the AD1868 audio DAC is its ability to
operate at reduced power supply voltages. This feature is very
important in portable battery operated systems. As the batteries
discharge, the supply voltage drops. Unlike any other audio
Figure 7. Recommended Circuit Schematic
NOISE REDUCTION CAPACITORS
The AD1868 has two noise reduction pins designated as NRL
(Pin 13) and NRR (Pin 11). It is recommended that external
noise reduction capacitors be connected from these pins to
AGND to reduce the output noise contributed by the voltage
reference circuitry. As shown in Figure 7, each of these pins
should be bypassed to AGND with a 4.7 µF or larger capacitor.
The connections between the capacitors, package pins and
AGND should be as short as possible to achieve the lowest
noise.
USING VBL AND VBR
The AD1868 has two bias voltage reference pins, designated as
VBR (Pin 8) and VBL (Pin 16). These pins supply a dc reference
voltage equal to the center of the output voltage swing. These
bias voltages replace “False Ground” networks previously required
in single-supply audio systems. At the same time, they allow dc-
coupled systems, improving audio performance.
Figure 8a illustrates the traditional approach used to generate
False Ground voltages in single-supply audio systems. This cir-
cuit requires additional power and circuit board space.
–VS 1
DGND 2
+VL 3
NC 4
16-BIT
LATCH
SERIAL
INPUT
REGISTER
CLK 5
LE 6
CONTROL
LOGIC
16-BIT
DAC
IOUT
16 +VS
15 TRIM
14
MSB
ADJ
13 IOUT
12 AGND
11 SJ
DATA 7
10 RF
NC 8
AD1851
NC = NO CONNECT
9 VOUT
Figure 8a. Schematic Using False Ground
REV. A
–5–
5 Page 
–VS 1
–VS 2
VOLTAGE
REFERENCE
TRIM 3
+VL 4
CLK 5
LE 6
DATA 7
INPUT
&
DIGITAL
OFFSET
–VL 8
AD1862
20-BIT
DAC
16 +VS
15 NR2
14 ADJ
13 NR1
12 AGND
11 IOUT
10 RF
9 DGND
AD1862 20-Bit, Low Noise Audio DAC
110 dB SNR Minimum
THD+N = 0.0019% (typical)
± 1 dB Gain Linearity
16-Pin Plastic DIP
AD1868
REV. A
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD1868.PDF ] | |
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