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PDF AD1870 Data sheet ( Hoja de datos )
| Número de pieza | AD1870 | |
| Descripción | Single-Supply 16-Bit Stereo ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Single-Supply
16-Bit ⌺-⌬ Stereo ADC
AD1870*
FEATURES
Single 5 V Power Supply
Single-Ended Dual-Channel Analog Inputs
92 dB (Typ) Dynamic Range
90 dB (Typ) S/(THD + N)
0.006 dB Decimator Passband Ripple
Fourth-Order, 64؋ Oversampling ⌺-⌬ Modulator
Three-Stage, Linear-Phase Decimator
256 ؋ fS or 384 ؋ fS Input Clock
Less than 100 W (Typ) Power-Down Mode
Input Overrange Indication
On-Chip Voltage Reference
Flexible Serial Output Interface
28-Lead SOIC Package
APPLICATIONS
Consumer Digital Audio Receivers
Digital Audio Recorders, Including Portables
CD-R, DCC, MD, and DAT
Multimedia and Consumer Electronics Equipment
Sampling Music Synthesizers
PRODUCT OVERVIEW
The AD1870 is a stereo, 16-bit oversampling ADC based on
sigma-delta (∑-∆) technology intended primarily for digital
audio bandwidth applications requiring a single 5 V power supply.
Each single-ended channel consists of a fourth-order one-bit
noise shaping modulator and a digital decimation filter. An on-
chip voltage reference, stable over temperature and time, defines
the full-scale range for both channels. Digital output data from
both channels are time-multiplexed to a single, flexible serial
interface. The AD1870 accepts a 256 × fS or a 384 × fS input
clock (fS is the sampling frequency) and operates in both serial
port “master” and “slave” modes. In slave mode, all clocks must
be externally derived from a common source.
Input signals are sampled at 64 × fS onto internally buffered
switched-capacitors, eliminating external sample-and-hold ampli-
fiers and minimizing the requirements for antialias filtering at the
input. With simplified antialiasing, linear phase can be preserved
across the passband. The on-chip single-ended to differential signal
converters save the board designer from having to provide them
externally. The AD1870’s internal differential architecture provides
increased dynamic range and excellent power supply rejection
characteristics. The AD1870’s proprietary fourth-order differen-
tial switched-capacitor ∑-∆ modulator architecture shapes the
*Protected by U.S. Patent Numbers 5055843, 5126653; others pending.
FUNCTIONAL BLOCK DIAGRAM
LRCK 1
WCLK 2
BCLK 3
DVDD1 4
DGND1 5
RDEDGE 6
S/M 7
384/256 8
AVDD 9
VINL 10
CAPL1 11
CAPL2 12
AGNDL 13
VREFL 14
SERIAL OUTPUT
INTERFACE
CLOCK
DIVIDER
THREE-STAGE FIR
DECIMATION
FILTER
THREE-STAGE FIR
DECIMATION
FILTER
DAC
DAC
DAC
DAC
SINGLE-TO-
SINGLE-TO-
DIFFERENTIAL INPUT DIFFERENTIAL INPUT
CONVERTER
CONVERTER
VOLTAGE
REFERENCE
AD1870
28 CLKIN
27 TAG
26 SOUT
25 DVDD2
24 DGND2
23 RESET
22 MSBDLY
21 RLJUST
20 AGND
19 VINR
18 CAPR1
17 CAPR2
16 AGNDR
15 VREFR
one-bit comparator’s quantization noise out of the audio pass-
band. The high order of the modulator randomizes the modulator
output, reducing idle tones in the AD1870 to very low levels.
Because its modulator is single-bit, the AD1870 is inherently
monotonic and has no mechanism for producing differential
linearity errors.
The input section of the AD1870 uses autocalibration to correct
any dc offset voltage present in the circuit, provided that the inputs
are ac-coupled. The single-ended dc input voltage can swing
between 0.7 V and 3.8 V typically. The AD1870 antialias input
circuit requires four external 470 pF NPO ceramic chip filter
capacitors, two for each channel. No active electronics are needed.
Decoupling capacitors for the supply and reference pins are
also required.
The dual digital decimation filters are triple-stage, finite impulse
response filters for effectively removing the modulator’s high
frequency quantization noise and reducing the 64 × fS single-bit
output data rate to an fS word rate. They provide linear phase
and a narrow transition band that properly digitizes 20 kHz signals
at a 44.1 kHz sampling frequency. Passband ripple is less than
0.006 dB, and stop band attenuation exceeds 90 dB.
(Continued on Page 7)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
AD1870
PIN FUNCTION DESCRIPTIONS
Input/ Pin
Pin Output Name
Description
1 I/O
LRCK
Left/Right Clock
2 I/O
WCLK Word Clock
3 I/O
BCLK Bit Clock
4I
5I
DVDD1 5 V Digital Supply
DGND1 Digital Ground
6I
7I
8I
RDEDGE Read Edge Polarity Select
S/M Slave/Master Select
384/256 Clock Mode
9I
10 I
11 O
AVDD
VINL
CAPL1
5 V Analog Supply
Left Channel Input
Left External Filter Capacitor 1
12 O
CAPL2 Left External Filter Capacitor 2
13 I
AGNDL Left Analog Ground
14 O
15 O
16 I
VREFL
VREFR
AGNDR
Left Reference Voltage Output
Right Reference Voltage Output
Right Analog Ground
17 O
18 O
CAPR2
CAPR1
Right External Filter Capacitor 2
Right External Filter Capacitor 1
19 I
20 I
21 I
22 I
23 I
VINR
AGND
RLJUST
MSBDLY
RESET
Right Channel Input
Analog Ground
Right/Left Justify
Delay MSB One BCLK Period
Reset
24 I
DGND2 Digital Ground
25 I
26 O
DVDD2
SOUT
5 V Digital Supply
Serial Data Output
27 O
TAG
Serial Overrange Output
28 I
CLKIN Master Clock
DEFINITIONS
Dynamic Range
The ratio of a full-scale output signal to the integrated output
noise in the passband (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/(THD + N)) 60 dB. Note that spurious har-
monics are below the noise with a –60 dB input, so the noise
level establishes the dynamic range. The dynamic range is speci-
fied with and without an A-Weight filter applied.
Signal to (Total Harmonic Distortion + Noise)
(S/(THD + N))
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the passband, expressed in decibels (dB).
Signal to Total Harmonic Distortion (S/THD)
The ratio of the rms value of the fundamental input signal to the
rms sum of all harmonically related spectral components in the
passband, expressed in decibels.
Passband
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Passband Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the passband,
expressed in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digi-
tal decimator’s filter to the degree specified by “stop band
attenuation.”
Gain Error
With a near full-scale input, the ratio of actual output to
expected output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per °C.
Midscale Offset Error
Output response to a midscale dc input, expressed in least-
significant bits (LSBs).
Midscale Drift
Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) per °C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds
(ms). More precisely, the derivative of radian phase with respect
to radian frequency at a given frequency.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (µs).
REV. 0
–5–
5 Page 
Shown in Figure 5 is a circuit for obtaining a 3 dB improve-
ment in dynamic range by using both channels of a single AD1870
with a mono input. A stereo implementation would require
using two AD1870s and using the recommended input structure
shown in Figure 2. Note that a single microprocessor would likely
be able to handle the averaging requirements for both left and
right channels.
SINGLE
CHANNEL
INPUT
AD1870
RECOMMENDED
INPUT BUFFER
VINR
AD1870
DIGITAL
AVERAGER
SINGLE
CHANNEL
OUTPUT
VINL
Figure 5. Increasing Dynamic Range By Using Two
AD1870 Channels
AD1870
DIGITAL INTERFACE
Modes of Operation
The AD1870’s flexible serial output port produces data in
two’s-complement, MSB-first format. The input and output sig-
nals are TTL-logic-level-compatible. Time multiplexed serial
data is output on SOUT (Pin 26), left channel then right chan-
nel, as determined by the left/right clock signal LRCK (Pin 1).
Note that there is no method for forcing the right channel to
precede the left channel. The port is configured by pin selec-
tions. The AD1870 can operate in either master or slave mode,
with the data in right-justified, I2S-compatible, Word Clock
controlled or left-justified positions.
The various mode options are pin-programmed with the S/M
(Slave/Master) Pin (7), the Right/Left Justify Pin (21), and the
MSBDLY Pin (22). The function of these pins is summarized
as follows:
S/M RLJUST MSBDLY WCLK
11
1
Output
11
0
Input
10
10
1
0
Output
Output
01
01
00
00
1
0
1
0
Output
Output
Output
Output
BCLK LRCK
Input Input
Input Input
Input Input
Input Input
Output Output
Output Output
Output Output
Output Output
Serial Port Operation Mode
Slave Mode. WCLK frames the data. The MSB is output on the
17th BCLK cycle. Provides right-justified data in slave mode
with a 64 × fS BCLK frequency. See Figure 7.
Slave Mode. The MSB is output in the BCLK cycle after
WCLK is detected HI. WCLK is sampled on the BCLK active
edge, with the MSB valid on the next BCLK active edge. Tying
WCLK HI results in I2S-justified data. See Figure 8.
Slave Mode. Data left-justified with WCLK framing the data.
WCLK rises immediately after an LRCK transition. The MSB is
valid on the first BCLK active edge. See Figure 9.
Slave Mode. Data I2S-justified with WCLK framing the data.
WCLK rises in the second BCLK cycle after an LRCK transi-
tion. The MSB is valid on the second BCLK active edge. See
Figure 10.
Master Mode. Data right-justified. WCLK frames the data,
going HI in the 17th BCLK cycle. BCLK frequency = 64 × fS.
See Figure 11.
Master Mode. Data right-justified + 1. WCLK is pulsed in the
17th BCLK cycle, staying HI for only 1 BCLK cycle. BCLK
frequency = 64 × fS. See Figure 12.
Master Mode. Data left-justified. WCLK frames the data.
BCLK frequency = 64 × fS. See Figure 13.
Master Mode. Data I2S-justified. WCLK frames the data.
BCLK frequency = 64 × fS. See Figure 14.
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD1870.PDF ] | |
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