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부품번호 AD28MSP02 기능
기능 Voiceband Signal Port
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AD28MSP02 데이터시트, 핀배열, 회로
a
FEATURES
Complete Analog I/O Port for Voiceband DSP
Applications
Linear-Coded 16-Bit Sigma-Delta ADC
Linear-Coded 16-Bit Sigma-Delta DAC
On-Chip Anti-Aliasing and Anti-lmaging Filters
On-Chip Voltage Reference
8 kHz Sampling Frequency
Twos Complement Coding
65 dB SNR + THD
Programmable Gain on DAC and ADC
Serial Interface To DSP Processors
24-Pin DlP/28-Lead SOIC
Single 5 V Power Supply
Voiceband Signal Port
AD28msp02
FUNCTIONAL BLOCK DIAGRAM
VOICEBAND
ANALOG
INPUT A
VOICEBAND
ANALOG
INPUT B
MUX
+20dB
AMP
VOLTAGE
REFERENCE
16-BIT
SIGMA-
DELTA ADC
DIGITAL
DATA AND
CONTROL
SERIAL
PORT
DIFFERENTIAL
ANALOG
OUTPUT
PGA
16-BIT
SIGMA-
DELTA DAC
GENERAL DESCRIPTION
The AD28msp02 Voiceband Signal Port is a complete analog
front end for high performance voiceband DSP applications.
Compared to traditional µ-law and A-law codecs, the
AD28msp02’s linear-coded ADC and DAC maintain wide
dynamic range while maintaining superior SNR and THD. A
sampling rate of 8.0 kHz coupled with 65 dB SNR + THD per-
formance make the AD28msp02 attractive in many telecom and
speech processing applications, for example digital cellular radio
and high quality telephones. The AD28msp02 simplifies overall
system design by requiring only a single +5 V power supply.
The inclusion of on-chip anti-aliasing and anti-imaging filters,
16-bit sigma-delta ADC and DAC, and programmable gain
amplifiers ensures a highly integrated and compact solution to
voiceband analog processing requirements. Sigma-delta conver-
sion technology eliminates the need for complex off-chip anti-
aliasing filters and sample-and-hold circuitry.
The AD28msp02’s serial I/O port provides an easy interface to
host DSP microprocessors such as the ADSP-2101, ADSP-2105
and ADSP-2111. The AD28msp02 is available in a 24-pin, 0.3"
plastic DIP and a 28-lead SOIC package.
FUNCTIONAL DESCRIPTION
Figure 1 shows a block diagram of the AD28msp02.
A/D CONVERSION
The A/D conversion circuitry of the AD28msp02 consists of two
analog input amplifiers, an optional 20 dB preamplifier, and
a sigma-delta analog-to-digital converter (ADC). The analog
input signal to the AD28msp02 must be ac-coupled.
Analog Input Amplifiers
The two analog input amplifiers (NORM, AUX) are internally
biased by an on-chip voltage reference in order to allow opera-
tion of the AD28msp02 with a single +5 V power supply.
An analog multiplexer selects either the NORM or AUX ampli-
fier as the input to the ADC’s sigma-delta modulator. The
optional 20 dB preamplifier may be used to increase the signal
level; the preamplifier can be inserted before the modulator or
can be bypassed. Input signal level to the sigma-delta modulator
should not exceed VINMAX, which is specified under “Analog
Interface Electrical Characteristics.” Refer to “Analog Input” in
the “Design Considerations” section of this data sheet for more
information.
The input multiplexer and 20 dB preamplifier are configured by
Bits 0 and 1 (IPS, IMS) of the AD28msp02’s control register. If
the multiplexer setting is changed while an input signal is being
processed, the ADC’s output must be allowed time to settle to
ensure that the output data is valid.
ADC
The ADC consists of a 2nd-order analog sigma-delta modulator,
an anti-aliasing decimation filter, and a digital high-pass filter.
The sigma-delta modulator noise-shapes the signal and pro-
duces 1-bit samples at a 1.0 MHz rate. This bit stream, which
represents the analog input signal, is fed to the anti-aliasing
decimation filter.
Decimation Filter
The anti-aliasing decimation filter contains two stages. The first
stage is a sinc4 digital filter that increases resolution to 16 bits
and reduces the sample rate to 40 kHz. The second stage is an
IIR low-pass filter.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703




AD28MSP02 pdf, 반도체, 판매, 대치품
AD28msp02
The IIR low-pass filter is a 10th-order elliptic filter with a pass-
band edge at 3.70 kHz and a stopband attenuation of 65 dB at
4 kHz. This filter has the following specifications:
Filter type:
Sample frequency:
Passband cutoff:*
Passband ripple:
Stopband cutoff:
Stopband ripple:
l0th-order low-pass elliptic IIR
40.0 kHz
3.70 kHz
± 0.2 dB
4.0 kHz
–65.00 dB
*The passband cutoff frequency is defined to be the last point in the passband
that meets the passband ripple specification.
(Note that these specifications apply only to this filter, and not to the entire
DAC. The specifications can be used to perform further analysis of the exact
characteristics of the filter, for example using a digital filter design software
package.)
Figure 2 shows the frequency response of the IIR low-pass filter.
Passband ripple is ± 0.2 dB for the combined effects of the
DAC’s digital filters (i.e., high-pass filter and IIR low pass of the
interpolation filter) in the 300 Hz–3400 Hz passband.
Analog Smoothing Filter and Programmable Gain Amplifier
The programmable gain amplifier (PGA) can be used to adjust
the output signal level by –15 dB to +6 dB. This gain is selected
by bits 7–9 (OG0, OG1, OG2) of the AD28msp02’s control
register.
The AD28msp02’s analog smoothing filter consists of a 2nd-
order Sallen-Key continuous-time filter and a 3rd-order
switched capacitor filter. The Sallen-Key filter has a 3 dB point
at approximately 80 kHz.
Differential Output Amplifier
The AD28msp02’s analog output (VOUTP, VOUTN) is pro-
duced by a differential output amplifier. The differential ampli-
fier can drive loads of 2 kor greater and has a maximum
differential output voltage swing of ± 3.156 V peak-to-peak
(3.17 dBm0). The output signal is dc-biased to the
AD28msp02’s on-chip voltage reference (VREF) and can be
ac-coupled directly to a load or dc-coupled to an external ampli-
fier. Refer to “Analog Output” in the “Design Considerations”
section of this data sheet for more information.
The VOUTP–VOUTN outputs must be used as differential out-
puts; do not use either as a single-ended output.
SERIAL PORT
The AD28msp02 communicates with a host processor via the
bidirectional synchronous serial port (SPORT). The SPORT is
used to transmit and receive digital data and control information.
All serial transfers are 16 bits long, MSB first. Data bits are
transferred at the serial clock rate (SCLK). SCLK equals the
master clock frequency divided by 5. SCLK = 2.6 MHz for the
master clock frequency MCLK = 13.0 MHz.
Host Processor Interface
The AD28msp02-to-host processor interface is shown in Figure 4.
AD28msp02
SDO
SDOFS
SCLK
DATA/CNTRL
SDI
SDIFS
Host Processor
SERIAL DATA RECEIVE
RECEIVE FRAME SYNC
SERIAL CLOCK
FLAG
SERIAL DATA TRANSMIT
TRANSMIT FRAME SYNC
Figure 4. AD28msp02-to-Host Processor Interface
Table I describes the SPORT signals and how they are used to
communicate with the host processor. The AD28msp02’s chip
select (CS) must be held high to enable SPORT operation. CS
can be used to 3-state the SPORT pins and disable communica-
tion with the host processor.
To use the ADSP-2101 or ADSP-2111 as host DSP processor
for the AD28msp02, the following connections can be used (as
shown in Figure 5):
AD28msp02 Pin
SCLK
SDO
SDOFS
SDI
SDIFS
DATA/CNTRL
ADSP-2101/2111 Pin
SCLK0
DR0
RFS0
DT0
TFS0
FO (Flag Output)
Signal
Name
SCLK
SDO
SDOFS
SDI
SDIFS
Description
Serial clock
Serial data output
Serial data output frame sync
Serial data input
Serial data input frame sync
Table I. SPORT Signals
Generated By
Signal State When
RESET Low (CS High)
AD28msp02
AD28msp02
AD28msp02
Host Processor
Host Processor
Low
Low
Low
Signal State During
Powerdown (CS High)
Active
Active*
Low
(CS must be held high to enable SPORT operation.)
*Outputs last data value that was valid prior to entering powerdown.
–4– REV. 0

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AD28MSP02 전자부품, 판매, 대치품
AD28msp02
Read Request
15 14 13
10
0
Table III. Control Word Read Format
12 11 10
000
98
00
7
0
65
00
43
00
210
000
Read Ready
15 14 13
11
0
12 11 10
000
98
00
7
0
65
00
43
00
210
000
Control Register Reads
To read the control register, the host processor must transfer
two control words. For each transfer, the DATA/CNTRL pin
must be low when SDIFS is asserted. If the MSB of the bit
stream is high, the SPORT recognizes the incoming serial data
as a request for control information. The protocol for reading
the control register is as follows:
1. The host processor sends a “Read Request” control word to
the AD28msp02. Since the MSB of this control word is high,
the SPORT recognized the incoming serial data as a read re-
quest and does not overwrite the control register.
2. When the AD28msp02 receives the read request, it finishes
any data transfers in progress and waits for a “Read Ready”
control word.
3. The host processor then transfers a “Read Ready” control
word to the AD28msp02. Upon receiving this control word,
the AD28msp02 transfers the control register contents to the
host processor via the SPORT.
4. When the SPORT completes the control register transfer, it
immediately resumes transmitting data at an 8 kHz rate.
This scheme allows any data transfers in progress to be com-
pleted and resolves any ambiguities between data and control
words. The format for the read control words is shown in
Table III.
DESIGN CONSIDERATIONS
Analog Input
The analog input signal to the AD28msp02 must be ac-coupled.
Figure 7 shows the recommended input circuit for the
AD28msp02’s analog input pin (either VINNORM or VINAUX).
The circuit of Figure 7 implements a first-order low-pass filter
with a 3 dB point at 20 kHz; this is the only filter that must be
implemented external to the AD28msp02 to prevent aliasing of
the sampled signal. Since the AD28msp02’s ADC uses a highly
oversampled approach that transfers the bulk of the anti-aliasing
filtering into the digital domain, the off-chip anti-aliasing filter
need only be of low order.
In the circuit shown in Figure 7, scaling of the analog input is
achieved by the resistors RIN and RFB. The input signal gain,
–RFB/RIN, can be adjusted from –12 dB to +26 dB by varying
the values of these resistors. The AD28msp02’s on-chip 20 dB
preamplifier can be enabled when there is not enough gain in
the input circuit; the preamplifier is configured by Bit 0 (IPS) of
the control register. Total gain must be configured to ensure
that a full-scale input signal (at CIN in Figure 7) produces a sig-
nal level at the input to the sigma-delta modulator of the ADC
that does not exceed VINMAX, which is specified under “Analog
Interface Electrical Characteristics.” If the total gain is increased
above unity, signal-to-noise (SNR + THD) performance will
not meet the listed specifications.
INPUT
SIGNAL
CIN
R IN
C FB
R FB
VFBNORM
VIN NORM
VFB AUX
VIN AUX
MUX
VOLTAGE
REFERENCE
AD28msp02
Figure 7. Recommended Analog Input Circuit
The dc biasing of the analog input signal is accomplished with
an on-chip voltage reference which nominally equals 2.5 V. The
input signal must be ac-coupled with an external coupling ca-
pacitor (CIN). CIN and RIN should be chosen to ensure a cou-
pling corner frequency of 30 Hz. CIN should be 0.1 µF or larger.
REV. 0
–7–

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