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부품번호 | A80186 기능 |
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기능 | HIGH-INTEGRATION 16-BIT MICROPROCESSORS | ||
제조업체 | Intel Corporation | ||
로고 | |||
전체 30 페이지수
80186 80188
HIGH-INTEGRATION 16-BIT MICROPROCESSORS
Y Integrated Feature Set
Enhanced 8086-2 CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-bit Timers
Programmable Memory and
Peripheral Chip-Select Logic
Programmable Wait State Generator
Local Bus Controller
Y Available in 10 MHz and 8 MHz
Versions
Y High-Performance Processor
4 Mbyte Sec Bus Bandwidth
Interface 8 MHz (80186)
5 Mbyte Sec Bus Bandwidth
Interface 10 MHz (80186)
Y Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I O
Y Completely Object Code Compatible
with All Existing 8086 8088 Software
10 New Instruction Types
Y Numerics Coprocessing Capability
Through 8087 Interface
Y Available in 68 Pin
Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier (LCC)
Y Available in EXPRESS
Standard Temperature with Burn-In
Extended Temperature Range
(b40 C to a85 C)
Figure 1 Block Diagram
272430 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1994
Order Number 272430-002
COPYRIGHT INTEL CORPORATION 1995
1
80186 80188
Leads Facing Up
Leads Facing Down
Figure 4 Plastic Leaded Chip Carrier
NOTE
Pin names in parentheses apply to the 80188
272430 – 4
4
4
4페이지 80186 80188
Table 1 Pin Descriptions (Continued)
Symbol
Pin
No
Type
Name and Function
RD QSMD 62
I O Read Strobe is an active LOW signal which indicates that the processor is
performing a memory or I O read cycle It is guaranteed not to go LOW
before the A D bus is floated An internal pull-up ensures that RD is HIGH
during RESET Following RESET the pin is sampled to determine whether
the processor is to provide ALE RD and WR or queue status information
To enable Queue Status Mode RD must be connected to GND RD will
float during bus HOLD
ARDY
55 I Asynchronous Ready informs the processor that the addressed memory
space or I O device will complete a data transfer The ARDY pin accepts a
rising edge that is asynchronous to CLKOUT and is active HIGH The
falling edge of ARDY must be synchronized to the processor clock
Connecting ARDY HIGH will always assert the ready condition to the CPU
If this line is unused it should be tied LOW to yield control to the SRDY pin
SRDY
49 I Synchronous Ready informs the processor that the addressed memory
space or I O device will complete a data transfer The SRDY pin accepts an
active-HIGH input synchronized to CLKOUT The use of SRDY allows a
relaxed system timing over ARDY This is accomplished by elimination of
the one-half clock cycle required to internally synchronize the ARDY input
signal Connecting SRDY high will always assert the ready condition to the
CPU If this line is unused it should be tied LOW to yield control to the
ARDY pin
LOCK
48 O LOCK output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW The LOCK signal is
requested by the LOCK prefix instruction and is activated at the beginning
of the first data cycle associated with the instruction following the LOCK
prefix It remains active until the completion of that instruction No
instruction prefetching will occur while LOCK is asserted When executing
more than one LOCK instruction always make sure there are 6 bytes of
code between the end of the first LOCK instruction and the start of the
second LOCK instruction LOCK is driven HIGH for one clock during RESET
and then floated
S0 52 O Bus cycle status S0 –S2 are encoded to provide bus-transaction
S1 53 O information
S2 54 O
Bus Cycle Status Information
S2 S1 S0
Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 Read I O
0 1 0 Write I O
0 1 1 Halt
1 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (no bus cycle)
The status pins float during HOLD
S2 may be used as a logical M IO indicator and S1 as a DT R indicator
NOTE
Pin names in parentheses apply to the 80188
7
7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ A80186.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
A80186 | HIGH-INTEGRATION 16-BIT MICROPROCESSORS | Intel Corporation |
A80188 | HIGH-INTEGRATION 16-BIT MICROPROCESSORS | Intel Corporation |
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