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A8351601F-40 데이터시트 PDF




AMIC Technology에서 제조한 전자 부품 A8351601F-40은 전자 산업 및 응용 분야에서
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부품번호 A8351601F-40 기능
기능 Bar Code Reader
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A8351601F-40 데이터시트, 핀배열, 회로
A8351601 Series
Bar Code Reader
Document Title
Bar Code Reader
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
1.0
History
Initial issue
Change document title from “Bar Code Reader” to
“8 Bit Microcontroller”
Error correction:
(1) Delete single-step operation description
(2) Delete “the only exit from power down is a hardware
reset” on page 32
Modify 44L QFP package outline drawing and dimensions
Modify PWM function
(1) Add PWM3 delay control bits D0, D1 and D2
(2) Add PWM4 output control bit PWM1.7
Error correction:
Delete Functional Description
Change document title from “8 Bit Microcontroller” to
“Bar Code Reader”
Modify AC, DC Electrical Characteristics:
Add 3V ± 10% condition
SFR Map address has some typewriting errors
Modify DC and AC Electrical Characteristics
Final version release
Issue Date
June 5, 2000
June 22, 2000
Remark
Preliminary
November 15, 2000
January 17, 2001
June 6, 2001
October 16, 2001
February 19, 2002
July 12, 2002
Final
(July, 2002, Version 1.0)
AMIC Technology, Inc.




A8351601F-40 pdf, 반도체, 판매, 대치품
Block Diagram
A8351601 Series
PSEN ALE EA RST
SFR
64KB
OTP
8KB
SRAM
TIMING AND
CONTROL
XTAL1 XTAL2
P0.0-P0.7
(AD0-AD7) P2.0-P2.7
A8-A15
OSCILLATOR
PORT 0
ADDRESS
PORT 2
ADDRESS
CPU
CORE
PWM
256B
RAM
TIMER 2
PORT 1
P1.0-P1.7
INTERRUPT
SERIAL PORT
TIMER 0.1
PORT 3
P3.0-P3.7
(July, 2002, Version 1.0)
3 AMIC Technology, Inc.

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A8351601F-40 전자부품, 판매, 대치품
A8351601 Series
Operating Description
The detail description of the A8351601 included in this
description are:
n Memory Map and Registers
n Timer/Counters
n Serial Interface
n Interrupt System
n Other Information
Memory Map and Registers
Memory
The A8351601 has separate address spaces for program
and data memory. The program and data memory can be
up to 64K bytes.
The A8351601 has 256 bytes of on-chip RAM, plus
numbers of special function registers. The lower 128 bytes
can be accessed either by direct addressing or by indirect
addressing. The upper 128 bytes can be accessed by
indirect addressing only. Figure 1 shows internal data
memory organization and SFR Memory Map.
FFH
Upper
128
80H
7FH
Lower
128
0
Accessible
by Indirect
Addressing
Only
Accessible
by Direct
and Indirect
Addressing
FFH
Accessible
by Direct
Addressing
80H
Special
Function
Registers
Ports,
Status and
Control Bits,
Timer,
Registers,
Stack Pointer,
Accumulator
(Etc.)
The lower 128 bytes of RAM can be divided into three
segments as listed below.
1. Register Banks 0-3: locations 00H through 1FH (32
bytes). The device after reset defaults to register bank 0.
To use the other register banks, the user must select
them in software. Each register bank contains eight 1-
byte registers R0-R7. Reset initializes the stack point to
location 07H, and is incremented once to start from 08H,
which is the first register of the second register bank.
2. Bit Addressable Area: 16 bytes have been assigned for
this segment 20H-2FH. Each one of the 128 bits of this
segment can be directly addressed (0-7FH). Each of the
16 bytes in this segment can also be addressed as a
byte.
3. Scratch Pad Area: 30H-7FH are available to the user as
data RAM. However, if the data pointer has been
initialized to this area, enough bytes should be left aside
to prevent SP data destruction.
Special Function Registers
The Special Function Registers (SFR's) are located in
upper 128 Bytes direct addressing area. The SFR Memory
Map in Figure 1 shows that.
F8
F0 B
E8
E0 ACC
D8
D0 PSW
C8 T2CON
C0
B8 IP
B0 P3
A8 IE
A0 P2
98 SCON
90 P1
88 TCON
80 P0
ADD
SBUF
TMOD
SP
RCAP2L RCAP2H
PWM1 PWM2
TL0
DPL
TL1
DPH
TL2
TH0
TH2
TH1
PCON
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
Bit
Addressable
Figure 1. Internal Data Memory and SFR Memory Map
Not all of the addresses are occupied. Unoccupied
addresses are not implemented on the chip. Read
accesses to these addresses in general return random
data, and write accesses have no effect.
User software should not write 1s to these unimplemented
locations, since they may be used in future
microcontrollers to invoke new features. In that case, the
reset or inactive values of the new bits will always be 0, and
their active values will be 1.
The functions of the SFRs are outlined in the following
sections.
Accumulator (ACC)
ACC is the Accumulator register. The mnemonics for
Accumulator-specific instructions, however, refer to the
Accumulator simply as A.
B Register (B)
The B register is used during multiply and divide
operations. For other instructions it can be treated as
another scratch pad register.
(July, 2002, Version 1.0)
6 AMIC Technology, Inc.

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부품번호상세설명 및 기능제조사
A8351601F-40

Bar Code Reader

AMIC Technology
AMIC Technology

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