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A83516L-12 데이터시트 PDF




AMIC Technology에서 제조한 전자 부품 A83516L-12은 전자 산업 및 응용 분야에서
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부품번호 A83516L-12 기능
기능 8 Bit Microcontroller
제조업체 AMIC Technology
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A83516L-12 데이터시트, 핀배열, 회로
Preliminary
Document Title
8 Bit Microcontroller
Revision History
Rev. No. History
0.0 Initial issue
A83516 Series
8 Bit Microcontroller
Issue Date
Remark
November 25, 1998 Preliminary
PRELIMINARY (November, 1998, Version 0.0)
AMIC Technology, Inc.




A83516L-12 pdf, 반도체, 판매, 대치품
A83516 Series
Pin Description
Pin No.
P-DIP
1-8
PLCC
2-9
Symbol
P1.0 - P1.7
9 10 RST
10 - 17
11,
13 - 19
P3.0 - P3.7
18 20 XTAL2
19 21 XTAL1
20
21 - 28
22
24 - 31
GND
P2.0 - P2.7
29 32 PSEN
30 33 ALE
31
32 - 39
35 EA
36 - 43 P0.7 - P0.0
40 44 VCC
Type
I/O
I/O
I
I
I/O
I
O
I
I
I
I
O
O
O
I
I
I/O
O
O
I
I/O
I
Description
Port1. Port1 is a bidirectional I/O port with internal pull-ups. Pin
P1.0 and P1.1 also provide alternate functions as follows:
P1.0 T2
Timer/Counter2 external input/clock out
P1.1 T2EX Timer/Counter2 capture/reload input
Reset input, active high. It must be kept high for at least two
machine cycles to be recognized by the processor
Port3. Port3 is a bidirectional I/O port with internal pull-ups. Port3
pins also serve alternate functions as follows:
P3.0 RXD Serial receive port
P3.1 TXD Serial transmit port
P3.2 INT0 External interrupt 0
P3.3 INT1 External interrupt 1
P3.4 T0
Timer/Counter 0 input
P3.5 T1
Timer/Counter 1 input
P3.6 WR
External data memory write strobe
P3.7 RD
External data memory read strobe
Crystal2. This is the output of crystal oscillator. It is the inversion
of XTAL1
Crystal1. This is the input of crystal oscillator. It can be driven by
an external clock
Ground
Port2. Port2 is a bidirectional I/O port with internal pull-ups. Port2
is also the multiplexed upper-order address bus during accesses
to external data memory
Program Store Enable : active low. The read strobe to external
program memory. PSEN is activated in each machine cycle
when fetching external program memory
Address Latch Enable : active high. ALE is used to enable the
address latch that separates the data on Port 0
External Access Enable : active low. It is held low to enable the
device to fetch code from external program memory
Port0. Port0 is an open drain, bidirectional I/O port. Port0 is also
the multiplexed low-order address bus during accesses to external
data memory
Power supply
PRELIMINARY (November, 1998, Version 0.0)
3
AMIC Technology, Inc.

4페이지










A83516L-12 전자부품, 판매, 대치품
AC Characteristics (TA = -25°C to + 85°C, VCC = 5V ± 10%)
Symbol
Parameter
Program Memory Cycle
tAP ALE Pulse Width
tALS Address Valid to ALE Low
tALH Address Hold from ALE Low
top PSEN Pulse Width
tAO ALE Low to PSEN Low
tOI2 PSEN Low to Valid Instruction in
tIDO Input Instruction Hold after PSEN High
tIFO Input Instruction Float after PSEN High
External Clock
fOPER
tCK3
tCKH4
tCKL4
Clock Frequency
Clock Period
Clock High Time
Clock Low Time
Data Memory Cycle
tPR RD Pulse Width
tPD RD Low to Valid Data in
tDHR Data Hold from RD High
tDFR Data Float from RD High
tAR ALE Low to RD Low
tWP WR Pulse Width
tDS Valid Data to WR Low
tDHW Data Hold from WR High
tAW ALE Low to WR Low
Serial Port Cycle
tSCK Serial Port Clock
tKI Clock Rising Edge to Valid Input Data
tIKH Input Data to Serial Clock Rising Clock Hold Time
tOKS Output Data to Serial Clock Rising Edge Setup Time
tOKH Output Data to Serial Clock Rising Edge Hold Time
1. This 20 ns is due to buffer driving delay and wire loading.
2. Instruction cycle time is 12 tck.
3. tck = 1/ foper
4. There are no duty cycle requirements on the XTAL1 input.
Min.
2tck – 201
1tck
1tck
3tck - 201
1tck
-
-
-
0
25
10
10
6tck - 201
-
0
0
3tck
6tck - 201
1tck
1tck
3tck
12tck
-
0
11tck
1tck
A83516 Series
Max.
-
-
-
-
-
2tck
1tck
1tck
40
-
-
-
-
4tck
2tck
2tck
3tck + 201
-
-
-
3tck + 201
-
11tck
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
MHZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PRELIMINARY (November, 1998, Version 0.0)
6
AMIC Technology, Inc.

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부품번호상세설명 및 기능제조사
A83516L-12

8 Bit Microcontroller

AMIC Technology
AMIC Technology

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