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AADG812YRU PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AADG812YRU
기능 0.5 CMOS 1.65 V to 3.6 V Quad SPST Switches
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AADG812YRU 데이터시트, 핀배열, 회로
FEATURES
0.5 Ω typ on resistance
0.8 Ω max on resistance at 125°C
1.65 V to 3.6 V operation
Automotive temperature range: –40°C to +125°C
High current carrying capability: 300 mA continuous
Rail-to-rail switching operation
Fast switching times: <25 ns
Typical power consumption < 0.1 µW
APPLICATIONS
Cellular phones
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communications systems
GENERAL DESCRIPTION
The ADG811, ADG812, and ADG813 are low voltage CMOS
devices containing four independently selectable switches.
These switches offer ultralow on resistance of less than 0.8 Ω
over the full temperature range. The digital inputs can handle
1.8 V logic with a 2.7 V to 3.6 V supply.
These devices contain four independent single-pole/single-
throw (SPST) switches. The ADG811 and ADG812 differ only
in that the digital control logic is inverted. The ADG811
switches are turned on with a logic low on the appropriate
control input, while a logic high is required to turn on the
switches of the ADG812. The ADG813 contains two switches
whose digital control logic is similar to the ADG811, while the
logic is inverted on the other two switches.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG813 exhibits break-before-make switching action.
The ADG811, ADG812, and ADG813 are fully specified for
3.3 V, 2.5 V, and 1.8 V supply operation. They are available in a
16-lead TSSOP package.
<0.5 Ω CMOS 1.65 V to 3.6 V
Quad SPST Switches
ADG811/ADG812/ADG813
FUNCTIONAL BLOCK DIAGRAMS
S1 S1 S1
IN1 IN1 IN1
D1 D1 D1
S2 S2 S2
IN2 IN2 IN2
ADG811
D2
S3
ADG812
D2
S3
ADG813
D2
S3
IN3 IN3 IN3
D3 D3 D3
S4 S4 S4
IN4 IN4 IN4
D4 D4 D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
PRODUCT HIGHLIGHTS
1. <0.8 Ω over full temperature range of –40°C to +125°C.
2. Single 1.65 V to 3.6 V operation.
3. Operational with 1.8 V CMOS logic.
4. High current handling capability (300 mA continuous
current at 3.3 V).
5. Low THD+N (0.02% typ).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.




AADG812YRU pdf, 반도체, 판매, 대치품
ADG811/ADG812/ADG813
Table 2. VDD = 2.5 V ± 0.2 V, GND = 0 V, unless otherwise noted1
Parameter
+25°C –40°C to +85°C –40°C to +125°C
ANALOG SWITCH
Analog Signal Range
0 V to VDD
On Resistance (RON)
0.65
0.72 0.8
0.88
On Resistance Match between
Channels (∆RON)
0.04
0.08
0.085
On Resistance Flatness (RFLAT(ON))
0.16
0.23 0.24
LEAKAGE CURRENTS
Source Off Leakage IS (OFF)
±0.2
±1 ±6
±35
Drain Off Leakage ID (OFF)
±0.2
±1 ±6
±35
Channel On Leakage ID, IS (ON)
±0.2
±1 ±11
±70
DIGITAL INPUTS
Input High Voltage, VINH
1.7
Input Low Voltage, VINL
0.7
Input Current, IINL or IINH
0.005
±0.1
CIN, Digital Input Capacitance
6
DYNAMIC CHARACTERISTICS2
tON 22
27 29
30
tOFF 4
67
8
Break-Before-Make Time Delay (tBBM) 18
(ADG813 only)
5
Charge Injection
25
Off Isolation
–67
Channel-to-Channel Crosstalk
–90
Total Harmonic Distortion (THD + N) 0.022
Insertion Loss
–3 dB Bandwidth
CS (OFF)
CD (OFF)
CD, CS (ON)
POWER REQUIREMENTS
IDD
–0.06
90
32
37
60
0.003
1.0
4
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
%
dB typ
MHz typ
pF typ
pF typ
pF typ
µA typ
µA max
Test Conditions/Comments
VDD = 2.3 V, VS = 0 V to VDD, IS = 10 mA;
Figure 18
VDD = 2.3 V; VS = 0.55 V, IS = 10 mA
VDD = 2.3 V; VS = 0 V to VDD, IS = 10 mA
VDD = 2.7 V
VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V;
Figure 19
VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V;
Figure 19
VS = VD = 0.6 V or 2.4 V; Figure 20
VIN = VINL or VINH
RL = 50 Ω, CL = 35 pF
VS = 1.5 V/ 0 V; Figure 21
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; Figure 21
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; Figure 22
VS = 1.25 V, RS = 0 Ω, CL = 1 nF;
Figure 23
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 24
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Figure 26
RL = 32 Ω, f = 20 Hz to 20 kHz,
VS = 1.5 V p-p
RL = 50 Ω, CL = 5 pF, f = 100 kHz
RL = 50 Ω, CL = 5 pF; Figure 25
VDD = 2.7 V
Digital inputs = 0 V or 2.7 V
1 Temperature range for the Y version is –40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 16

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AADG812YRU 전자부품, 판매, 대치품
ADG811/ADG812/ADG813
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN1 1
D1 2
S1 3
NC 4
GND 5
S4 6
D4 7
IN4 8
ADG811/
ADG812/
ADG813
TOP VIEW
(Not to Scale)
16 IN2
15 D2
14 S2
13 VDD
12 NC
11 S3
10 D3
9 IN3
NC = NO CONNECT
Figure 2.
Table 7. Terminology
Term
Definition
VDD
IDD
GND
Most positive power supply potential.
Positive supply current.
Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
VD, VS
RON
RFLAT (ON)
Analog voltage on Terminals D, S.
Ohmic resistance between D and S.
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the
specified analog signal range.
∆RON
IS (OFF)
ID (OFF)
ID, IS (ON)
VINL
VINH
IINL (IINH)
CS (OFF)
CD (OFF)
CD, CS (ON)
CIN
tON
tOFF
tBBM
Charge Injection
On resistance match between any two channels, i.e., RON max – RON min.
Source leakage current with the switch off.
Drain leakage current with the switch off.
Channel leakage current with the switch on.
Maximum input voltage for Logic 0.
Minimum input voltage for Logic 1.
Input current of the digital input.
Off switch source capacitance. Measured with reference to ground.
Off switch drain capacitance. Measured with reference to ground.
On switch capacitance. Measured with reference to ground.
Digital input capacitance.
Delay time between the 50% and the 90% points of the digital input and switch on condition.
Delay time between the 50% and the 90% points of the digital input and switch off condition.
On or off time measured between the 80% points of both switches, when switching from one to another.
A measure of the glitch impulse transferred from the digital input to the analog output during on-to-off switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.
–3 dB Bandwidth The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitudes plus noise of a signal to the fundamental.
Rev. A | Page 7 of 16

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AADG812YRU

0.5 CMOS 1.65 V to 3.6 V Quad SPST Switches

Analog Devices
Analog Devices

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