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PDF AAT3532IAS-T1 Data sheet ( Hoja de datos )
| Número de pieza | AAT3532IAS-T1 | |
| Descripción | MicroPower Microprocessor Reset Circuit | |
| Fabricantes | Advanced Analogic Technologies | |
| Logotipo |  |
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AAT3532
MicroPower™ Microprocessor Reset Circuit
General Description
The AAT3532 PowerManager™ product is a mem-
ber of AATI’s Total Power Management ICs™
(TPMIC™) product family. It is a fully integrated
device for monitoring microprocessor activity,
external reset, and power supply conditions. The
device holds the microprocessor in a reset condi-
tion for a minimum of 250ms while VCC is estab-
lished to ensure correct system start-up. A manual
reset can be initiated via a de-bounced input pin.
As an additional level of protection, the AAT3532
includes a watchdog timer which requires a period-
ic strobe input from the microprocessor to ensure
correct operation. The AAT3532 has a programma-
ble watchdog timer and voltage tolerance level.
The quiescent supply current is extremely low, typ-
ically 23µA.
The AAT3532 is available in an 8-pin SOP package
specified over -40° to 85°C temperature range.
Features
PowerManager™
• Adjustable 4.5V or 4.75V Voltage Monitor
• 250ms (min) Reset Pulse Width
• Low quiescent current: typically 23µA
• Adjustable Watchdog Timer (150ms, 600ms,
or 1200ms)
• De-bounced Manual Reset Input
• Operates down to 20ns strobe input pulse
width
• No external components
• Temp range -40° to 85°C
• Standard 8 pin SOP package
• Pin compatible with MAX1232
Applications
• Computers
• Controllers
• Telecom Equipment
• Embedded Systems
• Intelligent Instrumentation
• Automotive
Typical Application
VDD
VCC
PBRST
AAT3532
TD
TOL
GND
RST
RST
ST
VDD
RESET
INPUT
µP
I/O
3532.2001.11.0.9
1
1 page  
AAT3532
MicroPower™ Microprocessor Reset Circuit
Functional Block Diagram
VCC
TOL
VCC
Tolerance
Select
VREF
Reset
Generator
RST
RST
PBRST
ST
TD
De-Bounce
Circuit
Watchdog
Timer
Detector
Watchdog
Timer
GND
Applications Information
Power Monitor
The reset function monitors the VCC supply to ensure
a microprocessor is correctly reset and is powered
up into a known condition following a power supply
failure. RST and RST will remain valid for Vcc volt-
ages down to 1.4V.
The RST and RST pins are asserted whenever VCC
drops below the reset threshold voltage. This volt-
age can be set by programming the TOL pin.
Connecting TOL to VCC sets the 10% tolerance of
the VCC supply (typically 4.37V for VCC = 5V).
Connecting TOL to GND sets the 5% tolerance of
the VCC supply (typically 4.62V for VCC = 5V). The
reset pin is guaranteed to remain asserted for a
minimum period of 250ms after VCC has risen
above the reset threshold voltage.
RST output is an open drain output. For correct
operation, a pull-up resistor of 10kΩ should be con-
nected between this output and VCC.
VCC
0V
RESET output delay (VCC Rising)
tRPU
RST
+5V
+4.75V (5% Trip Point)
+4.50V (10% Trip Point)
RESET output delay (VCC Falling)
tRPD
RST
Figure 1. Reset Output Delay
3532.2001.11.0.9
5
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