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AB28F400BX-B90 데이터시트 PDF




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부품번호 AB28F400BX-B90 기능
기능 4-MBIT 256K x16/ 512K x8 BOOT BLOCK FLASH MEMORY FAMILY
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AB28F400BX-B90 데이터시트, 핀배열, 회로
A28F400BX-T B
4-MBIT (256K x16 512K x8) BOOT BLOCK FLASH
MEMORY FAMILY
Automotive
Y x8 x16 Input Output Architecture
A28F400BX-T A28F400BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
Y Optimized High Density Blocked
Architecture
One 16 KB Protected Boot Block
Two 8 KB Parameter Blocks
One 96 KB Main Block
Three 128 KB Main Blocks
Top or Bottom Boot Locations
Y Extended Cycling Capability
1 000 Block Erase Cycles
Y Automated Word Byte Write and Block
Erase
Command User Interface
Status Register
Erase Suspend Capability
Y SRAM-Compatible Write Interface
Y Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
Y Very High-Performance Read
90 ns Maximum Access Time
45 ns Maximum Output Enable Time
Y Low Power Consumption
25 mA Typical Active Read Current
Y Deep Power-Down Reset Input
Acts as Reset for Boot Operations
Y Automotive Temperature Operation
b40 C to a125 C
Y Write Protection for Boot Block
Y Hardware Data Protection Feature
Erase Write Lockout During Power
Transitions
Y Industry Standard Surface Mount
Packaging
JEDEC ROM Compatible
44-Lead PSOP
Y 12V Word Byte Write and Block Erase
VPP e 12V g5% Standard
Y ETOXTM III Flash Technology
5V Read
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290501-003




AB28F400BX-B90 pdf, 반도체, 판매, 대치품
A28F400BX-T B
For the A28F400BX Byte-wide or Word-wide In-
put Output Control is possible by controlling the
BYTE pin When the BYTE pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ 0 7 During the byte-
wide mode DQ 8 14 are tri-stated and DQ15 A-1
becomes the lowest order address pin When the
BYTE pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ 0 15
1 2 Applications
The 4-Mbit boot block flash memory family com-
bines high density high performance cost-effective
flash memories with blocking and hardware protec-
tion capabilities Its flexibility and versatility will re-
duce costs throughout the product life cycle Flash
memory is ideal for Just-In-Time production flow re-
ducing system inventory and costs and eliminating
component handling during the production phase
During the product life cycle when code updates or
feature enhancements become necessary flash
memory will reduce the update costs by allowing ei-
ther a user-performed code change via floppy disk
or a remote code change via a serial link The 4-Mbit
boot block flash memory family provides full func-
tion blocked flash memories suitable for a wide
range of automotive applications
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AB28F400BX-B90 전자부품, 판매, 대치품
A28F400BX-T B
1 4 A28F400BX Pin Descriptions
Symbol Type
Name and Function
A0 – A17
I ADDRESS INPUTS for memory addresses Addresses are internally latched during a write
cycle
A9 I ADDRESS INPUT When A9 is at 12V the signature mode is accessed During this mode A0
decodes between the manufacturer and device ID’s When BYTE is at a logic low only the
lower byte of the signatures are read DQ15 Ab1 is a don’t care in the signature mode when
BYTE is low
DQ0 – DQ7
I O DATA INPUTS OUTPUTS Inputs array data on the second CE and WE cycle during a
program command Inputs commands to the command user interface when CE and WE
are active Data is internally latched during the write and program cycles Outputs array
intelligent identifier and Status Register data The data pins float to tri-state when the chip is
deselected or the outputs are disabled
DQ8–DQ15 I O DATA INPUTS OUTPUTS Inputs array data on the second CE and WE cycle during a
program command Data is internally latched during the write and program cycles Outputs
array data The data pins float to tri-state when the chip is deselected or the outputs are
disabled as in the byte-wide mode (BYTE e ‘‘0’’) In the byte-wide mode DQ15 Ab1
becomes the lowest order address for data output on DQ0-DQ7
CE I CHIP ENABLE Activates the device’s control logic input buffers decoders and sense
amplifiers CE is active low CE high deselects the memory device and reduces power
consumption to standby levels If CE and RP are high but not at a CMOS high level the
standby current will increase due to current flow through the CE and RP input stages
RP I RESET POWER-DOWN Provides three-state control Puts the device in deep power-down
mode Locks the boot block from program erase
When RP is at logic high level and equals 6 5V maximum the boot block is locked and
cannot be programmed or erased
When RP e 11 4V minimum the boot block is unlocked and can be programmed or
erased
When RP is at a logic low level the boot block is locked the deep power-down mode is
enabled and the WSM is reset preventing any blocks from being programmed or erased
therefore providing data protection during power transitions When RP transitions from
logic low to logic high the flash memory enters the read array mode
OE I OUTPUT ENABLE Gates the device’s outputs through the data buffers during a read cycle
OE is active low
WE I WRITE ENABLE Controls writes to the Command Register and array blocks WE is active
low Addresses and data are latched on the rising edge of the WE pulse
BYTE
VPP
VCC
GND
I BYTE ENABLE Controls whether the device operates in the byte-wide mode (x8) or the
word-wide mode (x16) BYTE pin must be controlled at CMOS levels to meet 130 mA
CMOS current in the standby mode BYTE e ‘‘0’’ enables the byte-wide mode where data
is read and programmed on DQ0–DQ7 and DQ15 Ab1 becomes the lowest order address
that decodes between the upper and lower byte DQ8–DQ14 are tri-stated during the byte-
wide mode BYTE e ‘‘1’’ enables the word-wide mode where data is read and
programmed on DQ0–DQ15
PROGRAM ERASE POWER SUPPLY For erasing memory array blocks or programming
data in each block
Note VPP k VPPLMAX memory contents cannot be altered
DEVICE POWER SUPPLY (5V g 10%)
GROUND For all internal circuitry
NC NO CONNECT Pin may be driven or left floating
DU DON’T USE PIN Pin should not be connected to anything
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AB28F400BX-B90

4-MBIT 256K x16/ 512K x8 BOOT BLOCK FLASH MEMORY FAMILY

Intel Corporation
Intel Corporation

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